A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

Lütkemeier, Sven; Jungeblut, Thorsten; Berge, Hans Kristian Otnes; Aunet, Snorre; Porrmann, Mario; Rückert, Ulrich

doi:10.1109/jssc.2012.2220671

Cited by 73 publications

(32 citation statements)

References 32 publications

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“…The finished layout, including the main stage and the output buffer, of both LSs is shown in Fig. 2, with NLS having an area of 24.95 µm 2 and WLS occupying 21.38 µm 2 of an area. We evaluate both the LSs on the basis of the propagation delay ( p ), total energy-per-transition (E tr ), energy-delay-product (EDP), and static power dissipation (Ps).…”

Section: Resultsmentioning

confidence: 99%

“…Level shifter (LS) circuits are placed as an interface between a low voltage domain (V DDL ) and a high voltage domain (V DDH ) to convert a low voltage signal into higher levels. Sub-threshold operation has received recent attention as reduction of the supply voltage is one of the most effective knobs for low power battery operated devices [1,2]. Design of an LS circuit that can reliably convert sub-threshold input levels into a full V DDH signal with a minimum power and delay penalty in deep-submicron technologies is challenging [3], as conventional designs either require an unreasonable amount of area or incur higher static and dynamic power dissipation.…”

Section: Introductionmentioning

confidence: 99%

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Energy efficient low static-power voltage level shifter

Maroof

Sohail

Shin

2015

IEICE Electron. Express

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Level shifter circuits are necessary parts of modern SoCs, as they interface different voltage domain signals. This paper presents an energyefficient level up shifter capable of converting sub-threshold input signal to higher levels. The proposed design uses the feedback mechanism of a regulated gate cascode to achieve energy efficient operation. Once the desired output level is achieved, large static current does not flow, and static power is further minimized using a transistor stack. Implementing in a 90-nm process, post-layout simulation results show that the proposed level shifter has a propagation delay of 21.2 ns, a total energy-per-transition of only 77.5 fJ, and a static power dissipation of 7.2 nW.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Energy efficient low static-power voltage level shifter

Maroof

Sohail

Shin

2015

IEICE Electron. Express

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“…In addition, we perform gatelevel simulations (post synthesis and post place&route) to determine the energy consumption of the MPSoC. The accuracy of our RTL and gatelevel simulation flow has been verified by measurements of two ASIC prototypes [7]. Our ISS shows a simulation error of less than 1% compared to RTL simulator.…”

Section: Cycle Accurate Simulation (Cas)mentioning

confidence: 97%

“…2. Basic building block of the MPSoC is the VLIW CPU CoreVA that is designed to provide high resource efficiency [7]. According to the application domain, the number of VLIW slots, ALUs, multiplication, and division units can be configured at design time.…”

Section: Hardware Architecturementioning

confidence: 99%

Performance estimation of streaming applications for hierarchical MPSoCs

Flasskamp

Sievers

et al. 2016

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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Parallel programming and effective partitioning of applications for embedded many-core architectures requires optimization algorithms. However, these algorithms have to quickly evaluate thousands of different partitions. We present a fast performance estimator embedded in a parallelizing compiler for streaming applications. The estimator combines a single execution-based simulation and an analytic approach. Experimental results demonstrate that the estimator has a mean error of 2.6% and computes its estimation 2848 times faster compared to a cycle accurate simulator.

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“…Also, many digital blocks are operated in the sub-threshold regime to achieve energy efficiency for battery constraint devices [1,2]. Furthermore, many blocks exploit the use of dynamic voltage and frequency scaling (DVFS) to balance the load/utilization and the power consumption [3,4].…”

Section: Introductionmentioning

confidence: 99%

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

2017

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Multiple voltage domains are commonplace in modern SoCs and level shifter (LS) circuits allow different voltage domains to be interfaced with each other. As the reduced supply voltages are extensively used in digital blocks for low-power operation, the conversion of sub-threshold voltage levels to full VDD signal becomes a particular problem. In this paper we present a new LS structure for the fast and energy-efficient conversion of extremely low voltage levels. The proposed LS is a two-stage structure consisting of a controlled Wilson current mirror and eliminates the negative feedback mechanism. Inverted output of the second stage controls the current through the first stage. If the input signal is logical high (VDDL) then the circuit will produce high output (VDDH) and the first stage is prepared to conduct the current for logical 0 input (0V). This improves the slew rate problem and enables fast and energy-efficient operation. Considering process corners at a 90-nm technology node, the proposed design reliably converts 150-mV input signal into 1 V output signal. Post-layout results show that the proposed LS exhibits a propagation delay of 16 ns, a total energy per transition of only 79 fJ, and a static power dissipation of 16.6 nW for a 200 mV input signal at 1-MHz, while loading 100 fF of capacitive load. ARTICLE HISTORY

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A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

Cited by 73 publications

References 32 publications

Energy efficient low static-power voltage level shifter

Energy efficient low static-power voltage level shifter

Performance estimation of streaming applications for hierarchical MPSoCs

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

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