Performance estimation of streaming applications for hierarchical MPSoCs

Flasskamp, Martin; Sievers, Gregor; Ax, Johannes; Klarhorst, Christian; Jungeblut, Thorsten; Kelly, Wayne; Thies, Michael; Porrmann, Mario

doi:10.1145/2852339.2852342

Cited by 9 publications

(6 citation statements)

References 14 publications

(20 reference statements)

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“…Considering the calculation and communication cost of directed acyclic graph (DAG), Tang et al [8] presented two heuristic strategies based on integer linear programming to reduce communication overhead and scheduling length. Flasskamp et al [9] designed a performance estimator embedded in the compiler to partition and map streaming applications. For an MPSoC system consisting of a multi-core CPU and on-chip GPU, Vilches et al [10] introduced a novel framework that can adaptively find the best mapping for multiple tasks to achieve better performance.…”

Section: Related Workmentioning

confidence: 99%

Reliable and Energy-aware Mapping of Streaming Series-parallel Applications onto Hierarchical Platforms

Gou

Benoît

Chen

et al. 2020

2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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Streaming applications come from various application fields such as physics, and many can be represented as a series-parallel dependence graph. We aim at minimizing the energy consumption of such applications when executed on a hierarchical platform, by proposing novel mapping strategies. Dynamic voltage and frequency scaling (DVFS) is used to reduce the energy consumption, and we ensure a reliable execution by either executing a task at maximum speed, or by triplicating it. In this paper, we propose a structure rule to partition the series-parallel applications, and we prove that the optimization problem is NP-complete. We are able to derive a dynamicprogramming algorithm for the special case of linear chains, which provides an interesting heuristic and a building block for designing heuristics for the general case. The heuristics performance is compared to a baseline solution, where each task is executed at maximum speed. Simulations demonstrate that significant energy savings can be obtained.

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Section: Related Workmentioning

confidence: 99%

Reliable and Energy-aware Mapping of Streaming Series-parallel Applications onto Hierarchical Platforms

Gou

Benoît

Chen

et al. 2020

2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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“…Authors in [11,15,16] propose hybrid methods: first simulation is used to obtain the execution time of each procedure on each type of processing element, then analytical methods are used to account for cache and communication effects.…”

Section: Related Workmentioning

confidence: 99%

Elementary operations: a novel concept for source-level timing estimation

2019

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Early application timing estimation is essential in decision making during design space exploration of heterogeneous embedded systems in terms of hardware platform dimensioning and component selection. The decisions which have the impact on project duration and cost must be made before a platform prototype is available and software code is ready to be linked and thus timing estimation must be done using high-level models and simulators. Because of the ever increasing need to shorten the time to market, reducing the amount of time required to obtain the results is as important as achieving high estimation accuracy. In this paper, we propose a novel approach to source-level timing estimation with the aim to close the speed-accuracy gap by raising the level of abstraction and improving result reusability. We introduce a concept -elementary operations as distinct parts of source code which enable capturing platform behaviour without having the exact model of the processor pipeline, cache etc. We also present a timing estimation method which relies on elementary operations to craft hardware profiling benchmark and to build application and platform profiles. Experiments show an average estimation error of 5%, with maximum below 16%. ARTICLE HISTORY

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“…However, programming a complex MPSoC and making effective use of its resources is a challenging task for the programmer. For this reason we have developed a parallelizing compiler for streaming applications to assist in programming the CoreVA-MPSoC [6], [28]. This compiler, called CoreVA-MPSoC compiler, processes applications written in the StreamIt language [29].…”

Section: E Compiler Infrastructurementioning

confidence: 99%

“…A simple analytical model might be evaluated faster compared to a post place and route simulation but achieves a lower accuracy. Our approach is called Simulation Based Estimation (SBE) and combines a single execution-based simulation and an analytic approach [28]. The execution time of each tasks is measured only once and independent of MPSoC configuration and task placement, because all CPUs in our MPSoC have the same properties like, e.g., clock frequency and number of VLIW slots (cf.…”

Section: E Compiler Infrastructurementioning

confidence: 99%

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CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories

Sievers²,

Daberkow

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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Abstract-MPSoCs with hierarchical communication infrastructures are promising architectures for low power embedded systems. Multiple CPU clusters are coupled using an Network-onChip (NoC). Our CoreVA-MPSoC targets streaming applications in embedded systems, like signal and video processing. In this work we introduce a tightly coupled shared data memory to each CPU cluster, which can be accessed by all CPUs of a cluster and the NoC with low latency. The main focus is the comparison of different memory architectures and their connection to the NoC. We analyze memory architectures with local data memory only, shared data memory only, and a hybrid architecture integrating both. Implementation results are presented for a 28 nm FD-SOI standard cell technology. A CPU cluster with shared memory shows similar area requirements compared to the local memory architecture. We use post place and route simulations for precise analysis of energy consumption on both cluster and NoC level using the different memory architectures. An architecture with shared data memory shows best performance results in combination with a high resource efficiency. On average, the use of shared memory shows a 17.2% higher throughput for a benchmark suite of 10 applications compared to the use of local memory only. the communication infrastructure goes the on-chip memory architecture, which also has a huge impact on performance and energy efficiency. The main focus of this paper is the comparison of different memory architectures and their interaction with the NoC for many core systems. Compared to traditional processor systems, lots of many cores feature a different memory management, which changes the requirements on memory and NoC infrastructure. Traditional processor systems use a memory hierarchy with several (private and shared) on-chip caches, external DRAM, and a unified address space. This allows for easy programming, but results in unpredictable memory access times. Additionally, the cache logic and the coherence handling require a high amount of chip area and power. Therefore, a lot of Many-Core systems omit data caches and use software-managed scratchpad memories instead, which provide a resource-efficient alternative [1]. For performance reasons, the scratchpad memories are tightly attached to each CPU and communication between CPUs is initiated by software. In [2] we showed that area and power consumption of a single CoreVA CPU's data memory increases by 10%, when using a cache instead of scratchpad memory. Due to cache coherence issues it can be expected that these values will even increase for a cache-based many core system. Additionally, software-managed scratchpad memories gives full control of data communication to the programmer or an automatic partitioning tool (cf. Section III-E) and allows for a more accurate performance estimation.The many core architecture considered in this work is our CoreVA-MPSoC, which targets streaming applications in embedded and energy-limited systems. Examples for streaming applications are signal pr...

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Performance estimation of streaming applications for hierarchical MPSoCs

Cited by 9 publications

References 14 publications

Reliable and Energy-aware Mapping of Streaming Series-parallel Applications onto Hierarchical Platforms

Reliable and Energy-aware Mapping of Streaming Series-parallel Applications onto Hierarchical Platforms

Elementary operations: a novel concept for source-level timing estimation

CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories

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