Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign

Abstract

Many emerging products in communication, computing and consumer electronics demand that their functionality remains flexible also after the system has been manufactured and that is why the reconfiguration is starting to be considered into the design flow as a new relevant degree of freedom, in which the designer can have the system autonomously modify its functionalities according to the application's changing needs. Therefore, reconfigurable devices, such as FPGAs, introduce yet another degree of freedom in the design workflow: the designer can have the system autonomously modify the functionality carried out by the IP core according to the application's changing needs while it runs. Research in this field is, indeed, being driven towards a more thorough exploitation of the reconfiguration capabilities of such devices, so as to take advantage of them not only at compile-time, i.e. at the time when the system is first deployed, but also at run-time, which allows the reconfigurable device to be reprogrammed without the rest of the system having to stop running. This paper presents emerging methodologies to design reconfigurable applications, providing, as an example the workflow defined at the Politecnico di Milano.

Coordination of Independent Loops in Self-Adaptive Systems

“…Moreover, two similar GNU/Linux-based platforms with support for dynamic reconfiguration, with extensive details regarding the online support, are presented in Williams and Bergmann [2004], , Donato et al [2007], and Santambrogio and Sciuto [2008]. All these solutions proved to be quite effective: they can be used to monitor the system and to react to modification in the runtime environments but adjustments can be made only if they have been previously envisioned and studied at designed time.…”

RocketTC: A high throughput traffic classification architecture

“…RocketTC exploits the most advanced partial dynamic reconfiguration (PDR) [15] of FPGA technology to meet this requirement. Specifically, the classification engine array is partitioned into the static part and the dynamic part.…”

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

“…Based on the Register Transfer Level (RTL) SystemC, they implemented the specific operations for dynamic partial reconfiguration in the SystemC kernel. The DPRS design methodology proposed by DRESD [29] also included a SystemC-based design exploration framework [3], where the system functionalities were described using the Transaction Level Modeling (TLM) technique and mapped to a real system architecture. Instead of system verification using only simulation, an integrated design and verification methodology called Symbad [6] first described a reconfigurable system using SystemC for functional simulation.…”

“…Many existing hardware/software co-design methodologies [4,5,6,12,23,29,31] have proposed different effective and innovative approaches for the DPRS development; however, they only focus on parts of the DPRS development without supporting the full design and verification flow. As a result, there still exist many gaps in the DPRS development, even though they have many remarkable research results.…”