TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

Krishnan, Vyas; Katkoori, Srinivas

doi:10.1109/tvlsi.2009.2026047

Cited by 7 publications

(4 citation statements)

References 27 publications

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“…Thermal effects are another crucial issue in present‐day VLSI circuits due to increasing power densities that lead to elevated on‐chip peak temperatures. Krishnan and Katkoori 31 presented an SA‐based HLS and floorplanning method for energy and temperature‐aware IC designs. The experiments showed that the proposed method could lower peak on‐chip temperatures by 12% on average compared to traditional algorithms that only focus on average power optimization.…”

Section: Related Workmentioning

confidence: 99%

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Dilek,

Tosun,

Cakin

2023

Circuit Theory & Apps

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SummaryIntegrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error‐prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy‐based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High‐level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi‐objective optimization problem of finding a set of Pareto‐optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)‐based HLS methods for multi‐Vcc application‐specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)‐based and integer linear programming (ILP)‐based methods and showed their effectiveness in finding optimum or near‐optimum results in a short running time. SA‐based methods achieved up to 21.20% reliability improvement on average and up to 38% energy reduction on average, while preserving the reliability value against the GA‐based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.

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Section: Related Workmentioning

confidence: 99%

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Dilek,

Tosun,

Cakin

2023

Circuit Theory & Apps

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“…There are no public domain MPSoC programming benchmarks (BM) available for comparative studies. Previously, researchers have extensively used random task graphs generated from computer program [20,[26][27][28][29][30]32]. Consequently, we use task graphs for free [31], to generate a set of four random BMs for this study.…”

Section: Evaluation Frameworkmentioning

confidence: 99%

Game theoretic approach for run‐time task scheduling on an multi‐processor system on chip

Ganeshpure

Kundu

2013

IET Circuits, Devices & Systems

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Multi-processor system on chip (MPSoC) consists of multiple cores communicating via an on-chip communication backplane. An application to be executed on an MPSoC is represented using a task graph where a node represents an operation to be scheduled on a core and the edges represent the communication between these operations. Typically task graph scheduling on MPSoC is done statically during hardware-software co-design, based on estimated execution times. Static scheduling makes a program non-portable, hence dynamic scheduling is preferred. In this study, the authors present hardware-based dynamic feedback-driven task rescheduling heuristic that executes in real time. This task scheduling heuristic is based on the observation that during the course of execution, an application goes through a phase where a sub-graph (phase graph) of the application task graph repeatedly executes for a very large number of times. The proposed approach is iterative, where the schedule length of a phase graph converges to a smaller value in subsequent iterations. Experimental results show (i) real-time scheduling can be performed using proposed game theoretic approach which converges to a minimum in fewer than 100 iterations (ii) reducing the schedule length ranging 3-16% as compared with greedy heuristic.

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“…In the work of Krishnan and Katkoori, 9 a two‐stage simulated annealing‐based HLS technique was presented for power minimization with temperature‐aware scheduling and binding. Simulated annealing algorithm creates low‐power solution iteratively and minimizes on‐chip peak temperature by module‐level temperature estimation.…”

Section: Introductionmentioning

confidence: 99%

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

Rani

Kumar²

2019

Concurrency and Computation

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Summary Very‐large‐scale integration (VLSI) is a procedure of designing integrated circuit (IC) by linking number of transistors into single chip where attaining the higher accuracy is difficult task because of variation in process‐voltage‐temperature (PVT). This work presents Stochastic Spider Monkey Optimization–based High‐Level Synthesis (SSMO‐HLS) Model to improve the performance with better runtime adaptability. In SSMO‐HLS model, behavioral input is collected and dataflow analysis is carried out to convert input into dataflow diagram (DFD). Then, compilation process detects error functional unit (FU) in DFD. Spider monkey optimization is carried out to find optimal functional unit for performing allocation, scheduling, and binding process. After binding, output circuit gets generated with better runtime adaptability in case of PVT variations. The performance of SSMO‐HLS model is carried out using ISCAS'89 Benchmark Dataset where designed model increases FU selection accuracy and reduces error rate and circuit adaptability time when compared to state‐of‐the‐art works.

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TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

Cited by 7 publications

References 27 publications

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Game theoretic approach for run‐time task scheduling on an multi‐processor system on chip

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

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