With rising power densities in modern VLSI circuits, thermal effects are becoming important in the design of ICs. Elevated chip temperatures have an adverse impact on performance, reliability, power consumption, and cooling costs. To ensure adequate thermal management, all phases of the design flow must account for thermal effects on their design decisions. We present a two-stage simulated annealing-based high-level synthesis technique that combines power minimization with temperature-aware scheduling, binding, and floorplanning. In our technique, the first stage of the simulated annealing algorithm creates a low-power solution, which is then iteratively improved by the second stage to minimize estimated on-chip peak temperature using accurate module-level temperature estimation. We show that minimizing average power alone does not guarantee minimal peak temperatures. However, our approach consistently finds solutions that have lower on-chip peak temperatures and uniform on-chip temperature distributions, compared to a traditional low-power synthesis methodology that minimizes average power. Experiments show that our method reduces peak temperatures on average by 12% and up to 16%, compared to a traditional low-power synthesis algorithm that minimizes average power. These improvements in chip-level temperature distributions are achieved with a modest increase in chip area of under 15% on average.Index Terms-Behavioral synthesis, high-level synthesis (HLS), multistage simulated annealing, on-chip temperature variations, thermal hot spots, thermal management.
Recent progress in the fabrication of three-dimensional integrated circuits has opened up the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical synthesis for three-dimensional integrated is substantially different from traditional planar integrated circuits due to the presence of additional constraints of placing circuit blocks in multiple die. To realize the full potential offered by three-dimensional integrated circuits, high-level synthesis of these circuits must take layout-related issues unique to 3-D technology into account during the synthesis process. We present a 3-D layout aware binding algorithm for high-level synthesis that tightly integrates the synthesis tasks of resource binding, assignment of modules to multiple die, 3-D floorplanning, and inter-die via minimization. Since floorplanning and resource binding are interdependent, the algorithm can significantly outperform traditional high-level synthesis flows that seperate these tasks. Compared to a traditional 3-D layout-unaware binding, experiments show that our approach can improve the total wirelength by 29% on average, while the longest netlength is reduced by 21%. In addition, the number of through-die via count is reduced by 27%. These optimizations are achieved with no penalty in chip area.
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