Systematic exploitation of data parallelism in hardware synthesis of DSP applications

Abstract

In this paper, we describe an approach that we explored for low-power synthesis and optimization of digital signal, image, and video processing (DSP) applications. In particular, we consider the systematic exploitation of data parallelism across the operations of an application dataflow graph when synthesizing a dedicated hardware implementation. Data parallelism occurs commonly in DSP applications, and provides flexible opportunities to increase throughput or lower power consumption. Exploiting this parallelism in dedicated hardware implementation comes at the expense of increased resource requirements, which must be balanced carefully when applying the technique in a design tool. We propose a high level synthesis algorithm to determine the data parallelism factor for each computation, and based on the area and performance trade-off curve, design an efficient hardware representation of the dataflow graph. For performance estimation, our approach uses a cyclostatic dataflow intermediate representation of the hardware structure under synthesis. We then apply an automatic hardware generation framework to build the actual circuit. MOTIVATIONHigh-level synthesis has been of primary importance in the field of DSP as area and power considerations are critical in the DSP domain. Design space exploration can be done effectively from a high level description as some inherent traits are more obvious in the high level abstraction and become obscure in the low level implementations. Dataflow has proven to be an attractive high-level computation model for programming DSP applications. A restricted version of dataflow, termed synchronous dataflow (SDF), that offers strong compile-time predictability properties, has been studied extensively in the DSP context [1] [6]. We have developed an algorithm and Verilog code generation framework for optimal application of data-parallel hardware implementations to SDF graphs. Further, since , where is the operating voltage and is the operating frequency, we can reduce both and , thus trade performance for lower dynamic power consumption. As an example, we consider a simple 3-tap FIR filter. Figure 1 shows a synchronous dataflow graph representation of such a filter.Here, the inputs to each module consume one unit of data upon each invocation, and the modules produce one unit of data at the output. From this SDF graph representation of the filter, we can clearly see that data parallelism through replication of hardware blocks can be used for each of the modules to increase the throughput. The given dataflow graph provides enough information to derive a hardware implementation of the filter. But by analyzing the given dataflow, we can increase the throughput of the circuit by duplicating the multipliers and creating parallel datapaths to them. Figure 2 shows the 3-tap FIR filter of Figure 1 with data-parallel factors of and for the multipliers and the adders respectively. The additional switches needed for sending data to multiple instances of the modules are also shown. This possi...

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