Reconfigurable image registration on FPGA platforms

Abstract

Image registration is computationally intensive, and hence difficult to implement in real-time. In recent efforts, image registration algorithms have been implemented in field-programmable gate array (FPGA) technology to improve performance, while providing programmability and dynamic reconfigurability. In this paper, we present a novel architecture for dynamically-reconfigurable image registration, along with details on the methodology used to derive the architecture. Unlike previous FPGA implementations for image registration, the architecture developed in this paper tunes its parallel processing structure adaptively based on relevant characteristics of the input images.

Model-Based Mapping of Image Registration Applications onto Configurable Hardware

“…A dynamically-reconfigurable FPGA implementation was proposed based on the PVV metric in [8]. We considered intervoxel parallelism along with intra-voxel parallelism, and we developed a comparison of the associated performance gains in [8].…”

“…We considered intervoxel parallelism along with intra-voxel parallelism, and we developed a comparison of the associated performance gains in [8].…”

Reconfigurable acceleration of 3D image registration

“…With a streaming interface and coupling with high level descriptions in MATLAB, this developing environment enables fast and optimized implementations on medical image processing. An FPGA based mutual information evaluation system for IR is proposed in [4]. The system utilizes a data flow model to improve hardware parallelism by sub-volume division.…”

Model-based mapping of a nonrigid image registration algorithm to heterogeneous architectures

“…In [18], Sen et al presented a scheme that utilizes intra-and inter-voxel parallelization to optimize the coordinate transformation unit. Among actors C, D, E and F we find the same degree of intra voxel parallelization.…”