Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran, Ramon; Buyuktosunoglu, Alper; Gupta, Manav; González, Marc; Bose, Pradip

doi:10.1109/micro.2012.27

Cited by 40 publications

(20 citation statements)

References 46 publications

(112 reference statements)

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“…We demonstrated that validating a power model at the core or chip level hides a large amount of internal error at the unit level and below. Targeted microbenchmarking is a well-known technique for characterizing fine-grained power [1,27,45]. 2.…”

Section: Discussion and Guidelinesmentioning

confidence: 99%

Quantifying sources of error in McPAT and potential impacts on architectural studies

Jacobson

Bose

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Architectural power modeling tools are widely used by the computer architecture community for rapid evaluations of high-level design choices and design space explorations. Currently, McPAT [31] is the de facto power model, but the literature does not yet contain a careful examination of its modeling accuracy. In addition, the issue of how greatly power modeling error can affect architectural-level studies has not been quantified before. In this work, we present the first rigorous assessment of McPAT's core power and area models with a detailed, validated power modeling toolchain used in current industrial practice. We find that McPAT's predictions can have significant error because some of the models are either incomplete, too high-level, or assume implementations of structures that differ from that of the core at hand. We demonstrate that large errors are possible when using McPAT's dynamic power estimates in the context of voltage noise and thermal hotspots, but for steady-state properties, accurately modeling leakage power is more important. Based on our analysis, we are able to provide guidelines for creating accurate McPAT models, even without access to detailed industrial power modeling tools. We conclude that in spite of its accuracy gaps, McPAT is still a very useful tool for many architectural studies, and its limitations can often be adequately addressed for a given research study of interest.

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Section: Discussion and Guidelinesmentioning

confidence: 99%

Quantifying sources of error in McPAT and potential impacts on architectural studies

Jacobson

Bose

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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“…Activity proxies constitute a well-known technique to estimate or track the power consumption profile of processor chips [12][13][14][15][16]. In the z13 design, they consist of a set of 16 activity counters.…”

Section: Activity Proxiesmentioning

confidence: 99%

“…The methodology is centered around the use of an automated microbenchmark generation toolset called MicroProbe [12].…”

Section: Power-management Characterization Through Automated Microbenmentioning

confidence: 99%

“…Manual, expert-driven generation (and fine-tuning) of such stressmarks can be a tedious and error-prone process. To overcome these issues, we used the MicroProbe [12] framework to systematically generate the stressmarks required during the z13 post-silicon test/ bring-up process. Automation in stressmark generation has been attempted by other research groups, but as discussed in [12], MicroProbe has significant new features, tested in real machine contexts, that have not been available before.…”

Section: Overviewmentioning

confidence: 99%

“…To overcome these issues, we used the MicroProbe [12] framework to systematically generate the stressmarks required during the z13 post-silicon test/ bring-up process. Automation in stressmark generation has been attempted by other research groups, but as discussed in [12], MicroProbe has significant new features, tested in real machine contexts, that have not been available before. The recent work of Kim et al [18] is an example of inductive noise stress test generation that was used in an AMD processor context.…”

Section: Overviewmentioning

confidence: 99%

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Robust power management in the IBM z13

et al. 2015

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The power management strategy adopted for the IBM z13i processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systemsi application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

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