Quantifying sources of error in McPAT and potential impacts on architectural studies

Xi, Sam Likun; Jacobson, Hans; Bose, Pradip; Wei, Gu-Yeon; Brooks, David

doi:10.1109/hpca.2015.7056064

Cited by 79 publications

(44 citation statements)

References 48 publications

(53 reference statements)

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“…We incorporate the changes suggested by Xi et al [22] to improve the accuracy of the models. The hardware structures of the DMU are modeled using CACTI 6.0 [23], adding the appropriate counters in gem5 to measure the extra power introduced by the DMU.…”

Section: Experimental Framework a Full-system Simulation Infrastmentioning

confidence: 99%

Architectural Support for Task Dependence Management with Flexible Software Scheduling

Castillo

Alvarez

Moretó³

et al. 2018

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Abstract-The growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its programmability, portability and potential for optimizations. However, with the expected increase in core counts, fine-grained tasking is required to exploit the available parallelism, which increases the overheads introduced by the runtime system. This work presents Task Dependence Manager (TDM), a hardware/software co-designed mechanism to mitigate runtime system overheads. TDM introduces a hardware unit, denoted Dependendence Management Unit (DMU), and minimal ISA extensions that allow the runtime system to offload costly dependence tracking operations to the DMU and to still perform task scheduling in software. With lower hardware cost, TDM outperforms hardware-based solutions and enhances the flexibility, adaptability and composability of the system. Results show that TDM improves performance by 12.3% and reduces EDP by 20.4% on average with respect to a software runtime system. Compared to a runtime system fully implemented in hardware, TDM achieves an average speedup of 4.2% with 7.3x less area requirements and significant EDP reductions. In addition, five different software schedulers are evaluated with TDM, illustrating its flexibility and performance gains. I. INTRODUCTIONThe end of Dennard scaling [1] and the subsequent stagnation of the CPU clock frequency has caused a dramatic increase in the core counts of multi-cores [2]. To fully exploit these large core counts in an efficient way, the hardware and the software stack must collaborate to avoid performance problems such as load imbalance or memory bandwidth exhaustion, while improving energy efficiency.The growing complexity of multi-cores has brought sophisticated software mechanisms aiming at optimally managing parallel workloads. One of the most extended approaches is task-based programming models, such as OpenMP 4.0 [3], that apply a data-flow execution model to orchestrate the execution of the parallel tasks respecting their control and data dependences. These programming models are a very appealing solution to program complex multicores due to their benefits in performance, programmability, cross-platform flexibility, and potential for applying generic optimizations at the runtime system level [4]- [9].A key aspect of this execution model is the granularity of the tasks. Fine-grain parallelism exposes large degrees of

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Section: Experimental Framework a Full-system Simulation Infrastmentioning

confidence: 99%

Architectural Support for Task Dependence Management with Flexible Software Scheduling

Castillo

Alvarez

Moretó³

et al. 2018

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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“…Power consumption is evaluated with McPAT [23] using a process technology of 22 nm, voltage of 0.6V and the default clock gating scheme. We add the changes suggested by Xi et al [24] to improve the accuracy of the models. The hardware structures of RaCCD are modeled using CACTI 6.0 [25].…”

Section: A Full-system Simulation Infrastructurementioning

confidence: 99%

Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs

Caheny

Alvarez

Valero

et al. 2018

SC18: International Conference for High Performance Computing, Networking, Storage and Analysis

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With increasing core counts, the scalability of directory-based cache coherence has become a challenging problem. To reduce the area and power needs of the directory, recent proposals reduce its size by classifying data as private or shared, and disable coherence for private data. However, existing classification methods suffer from inaccuracies and require complex hardware support with limited scalability. This paper proposes a hardware/software co-designed approach: the runtime system identifies data that is guaranteed by the programming model semantics to not require coherence and notifies the microarchitecture. The microarchitecture deactivates coherence for this private data and powers off unused directory capacity. Our proposal reduces directory accesses to just 26% of the baseline system, and supports a 64× smaller directory with only 2.8% performance degradation. By dynamically calibrating the directory size our proposal saves 86% of dynamic energy consumption in the directory without harming performance.

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“…Estimating power with this tool is slow as they require use of a cycle-accurate simulator such as GEM5 [2] to acquire the data needed by the power model. Recently, Xi et al [19] found that McPAT's estimations might have a significant error due to some of their power models being incomplete, or too highlevel, or assume implementations of structures that differ from that of the real hardware. The Functional-Level Power Analysis (FLPA) technique proposed by Rethinagiri et al [14][13] [15] was efficiently utilized in developing power models for various hardware components (processing core, clock unit, memory system, Input/Output peripheral units, etc.)…”

Section: Related Workmentioning

confidence: 99%

VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes

Rethinagiri¹,

Palomar²,

Moreno³

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Power and energy consumption of data centers are steadily increasing and the work performed by the data centers is not proportional to the power dissipated, where every μA is a revenue for the entity. On the one hand, the hardware community is proposing various methodologies to address this issue such as low-power processors, heterogeneity, etc. to reduce the power of the servers. On the other hand, the software community proposes mechanisms such as virtual machines (VMs), work-load scheduling, etc. to increase the utilization of the processor. In order to properly evaluate the impact of these mechanisms, we need an accurate power monitoring and estimation tool at the hardware host level, the VM level and the system-level. This paper proposes a novel power monitoring middleware on a low-power platform at the node level (ARM Big.LITTLE) and an estimation methodology by using a simulator for future data center prototypes at any given level of virtualization. First, we built an instrumentation framework to measure the power based on hardware counter activities and with respect to current fluctuation. This allows us to build power models for the corresponding platforms, which are fed into the middleware to estimate power on the fly. Furthermore, we used the same framework for future low-power processors such as ARM Cortex -A57 and -A53 based platforms, which are integrated into the architectural simulator by providing an API to estimate power with the power model. Second, we present a machine learningbased energy efficient scheduling of the VMs that leverages VPM. The results obtained with the power monitoring middleware differ less than 2% from real board measurements and 5% when using the simulation environment regardless of the number of virtual machines used. Furthermore, we reduced 40% of energy consumption on average when compared to default scheduling of the KVM hypervisor.

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Quantifying sources of error in McPAT and potential impacts on architectural studies

Cited by 79 publications

References 48 publications

Architectural Support for Task Dependence Management with Flexible Software Scheduling

Architectural Support for Task Dependence Management with Flexible Software Scheduling

Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs

VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes

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