System, process, and design implications of a reduced supply voltage microprocessor

Abstract

This paper describes the system, process and design implications of converting a microprocessor chipset originally implemented in a 5V 1.5/lin (drawn) CMOS proce"" tu olle implemented in a 3.3V 1.0",m (drawn) CMOS process. The chipset is 75% faster than the previous generation and is comprised of a processor chip, a floating point chip. a cache controller chip, and a clock chip!. It operates at 62.5MHz under worst·case conditions. Fig ures 1·4 contain micrographs of each dcsign_ Table 1 describes power and packaging spccifications for each ch ip. Table 2 de scribes the 3.3V 1.0/-lm (drawn) process specifications. Figure 5 shows a high-temperature schmoo plot for the CPU chip.The 1",m/3.3V process is derived from the 1.5/-1m/5V pro cess by scaling down all lateral dimensions and the gate oxide by 67% and reducing VT's proportionally with supply voltage. The supply voltage is reduced primarily to reduce overall power con sumption but also to improve reliability. Other process enhance ments include a third level of AI interconnect, low-resistance source drains, and precision resistors_ The third level of metal is added for improved power distribution and to maintain accept able electrical integrity. The TiN component of Yletal-3 can also act as a fuse layer if redundancy is incorporated in the design.When optimized, this 3.3 V process is as fast as a comparable 5V proC"". The change in VT necessitates extreme care in de signing dynamic circuits subject to absolute noise. such as input buffers, even though TTL level conversion is much simpler. The clock-chip oscillator input provides an example. A differential ECL oscillator is ac coupled to the oscillator input. Pullup and pulldown resistors of equ al valuc arc used to bias the input to VOO/2. Thc input is then fed directly into the differential amp lifier, as shown in Figure 6. The circuit is able to resolve a vol tage difference of 300m V.As a result of the Tox reduction, an on-chip decoupling capacitur ring (.012",F) is added for improved signal integrity.The ring must supply sufficient charge during each 4ns phase to decouple all switching events. The capacitor is implemented as parallel NMOS devices with VDO attached to the gate and YSS attached to both source and drain. The dimensions of the device (12.5/-1m channel length by 150/-lm channel width) are chosen to maximize gate area and limit worst-case RC delay to 0.16ns in both poly-silicon and the channel. Internal nuise is reduced by 750/. at the ('xpense of a predicted 3.7'/0 yield reductiun.Reduced geometries make it possible to increase the size of a number of arrays in the chipset. Row redundancv is added to the on-chip cache for improved yield. The TiN Mctal-3 fuse circuit desi�ned for laser programming during wafer sort is shown in Figure 7. In a processor chip, a fraction 0[' the area is devoted to the cache array and therefore adding redundancy can only increase the overall yield to the level of the remaining non cache logic. Yield analysis shows that addin� row redun dancy to the cache design coul...

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