HCNC: High Capacity Netlist Compare

Abstract

Netlist comparison is a critical component of the VLSl layout verification process. Present techniques for netlist comparison effectively solve this problem for small to medium size designs, but fail for large designs due to memory limitations. This paper describes HCNC, High Capacity Netlist Compare ; a technique for netlist comparison that uses the natural hierarchy of the transistor circuit to significantly increase the capacity of traditional netlist comparison algorithms. Since the natural hierarchy of the circuit is used, HCNC does not require hierarchical information from the user. Results from the network comparison of several large industrial circuits shall show the viability of this algorithm.