PRISC software acceleration techniques

Razdan, Rahul; Brace, Karl; Smith, Michael D.

doi:10.1109/iccd.1994.331875

Cited by 30 publications

(12 citation statements)

References 10 publications

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“…Another category of reconfigurable architectures presents much tighter integration. Examples are ConCise [11], PRISC [12] and Chimaera [13]. In these architectures, the reconfigurable units are deeply embedded into the pipeline of the processor.…”

Section: Related Workmentioning

confidence: 99%

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Mei

Vernalde

Verkest

et al. 2003

Lecture Notes in Computer Science

414

218

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Abstract. The coarse-grained reconfigurable architectures have advantages over the traditional FPGAs in terms of delay, area and configuration time. To execute entire applications, most of them combine an instruction set processor (ISP) and a reconfigurable matrix. However, not much attention is paid to the integration of these two parts, which results in high communication overhead and programming difficulty. To address this problem, we propose a novel architecture with tightly coupled very long instruction word (VLIW) processor and coarse-grained reconfigurable matrix. The advantages include simplified programming model, shared resource costs, and reduced communication overhead. To exploit this architecture, our previously developed compiler framework is adapted to the new architecture. The results show that the new architecture has good performance and is very compiler-friendly.

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Section: Related Workmentioning

confidence: 99%

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Mei

Vernalde

Verkest

et al. 2003

Lecture Notes in Computer Science

414

218

View full text Add to dashboard Cite

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“…Fine-grained architectures include the PRISC work [2,4]. PRISC was proposed to be a simple, pipelined, single-issue processor augmented with a single PFU.…”

Section: Prior Workmentioning

confidence: 99%

“…PRISC, the first architecture with fine-grained configurable hardware units, was proposed by Razdan and Smith [2,4]. This architecture includes programmable functional units, or PFUs, attached directly to the datapath of a simple pipelined, single-issue in-order processor.…”

Section: Introductionmentioning

confidence: 99%

Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Zhang

Martonosi

2000

Lecture Notes in Computer Science

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Abstract. The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, however, are limited by a need for generality and for streamlined implementation. The particular needs of one application are balanced against the needs of the full range of applications considered. For this reason, one can "design" a better instruction set when considering only a single application than when considering a general collection of applications. Configurable hardware gives us the opportunity to explore this option. This paper examines the potential for automatically identifying application-specific extended instructions and implementing them in programmable functional units based on configurable hardware. Adding fine-grained reconfigurable hardware to the datapath of an out-of-order issue superscalar processor allows 4-44% speedups on the MediaBench benchmarks [1]. As a key contribution of our work, we present a selective algorithm for choosing extended instructions to minimize reconfiguration costs within loops. Our selective algorithm constrains instruction choices so that significant speedups are achieved with as few as 4 moderately sized programmable functional units, typically containing less than 150 look-up tables each.

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“…• RPUs acting like an extended data-path of the processor (Figure 1-6.d) such as the OneChip [16], the PRISC -Programmable Reduced Instruction Set Computer [14], and the Chimaera [5]. …”

Section: Couplingmentioning

confidence: 99%

Introduction to Reconfigurable Hardware

Masselos

Voros

System Level Design of Reconfigurable Systems-on-Chip

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Abstract:This chapter introduces the reader to main concepts of reconfigurable computing and reconfigurable hardware. Different types of reconfiguration are discussed. A detailed classification of reconfigurable architectures with respect to the granularity of their building blocks, the reconfiguration scheme and the system level coupling is also presented.Key words: Reconfigurable hardware, reconfigurable architectures, reconfiguration, reconfigurable computing RECONFIGURABLE COMPUTING AND RECONFIGURABLE HARDWAREReconfigurable computing refers to systems incorporating some form of hardware programmability-customizing how the hardware is used using a number of physical control points [2]. These control points can then be changed periodically in order to execute different applications using the same hardware. Reconfigurable hardware offers a good balance between implementation efficiency and flexibility as shown in Figure 1-1. This is because reconfigurable hardware combines post-fabrication programmability with the spatial (parallel) computation style [2] of application specific integrated circuits (ASICs), which is more efficient in comparison to the temporal (sequential) computation style of instruction set processors.Due to the increasing flexibility requirements (e.g. for adaptation to different evolving standards and operating conditions) that are imposed by computationally intensive applications such as wireless communications,

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PRISC software acceleration techniques

Cited by 30 publications

References 10 publications

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Introduction to Reconfigurable Hardware

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