Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance

Larsson, Patrik

doi:10.1109/4.563679

Cited by 47 publications

(9 citation statements)

References 8 publications

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“…Figure 7.26 depicts the distributed RC model of the MOS transistor and the equivalent circuit model of the discrete decoupling capacitors with an ESL of 90 pH, a capacitance of 0.47 lF, and dimensions of 1.0 9 0.5 9 0.25 mm. The on-chip MOS decoupling capacitor can be modeled by including the series connection of a frequency-dependent C_decap (Cn) and ESR (Rn) in the unit-cell model of the on-chip PDN [29]. The gate length and channel width of the NMOS capacitor used for analyzing the PDN impedance were 30 and 315 nm, respectively.…”

Section: Modeling Of the Chip-pdn Tsv And Decouplingmentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

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Section: Modeling Of the Chip-pdn Tsv And Decouplingmentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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“…The most area-efficient realization of on-chip capacitance in a standard digital CMOS process is to use the gate capacitance of MOS transistors [7]. The gate serves as one plate, and other three terminals serve as the other plate by connecting together to the ground or to the voltage source, as shown in Figure 3.…”

Section: Realizations Of the Designed Capacitancesmentioning

confidence: 99%

Low swing drivers based on charge redistribution

Fengfeng

Jia

Wang

et al. 2010

Sci. China Inf. Sci.

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Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing drivers scheme based on charge redistribution is proposed. Significant reduction in power dissipation is achieved by dividing the full signal swing into several lower ones. The proposed circuits are especially suitable for driving multi-branch transmission wires by utilizing higher efficiency of charges. Compared with the reference design, the new scheme can reduce power dissipation by more than 66% as shown by HSPICE simulation while driving three branches. The proposed circuits have been fabricated and its effectiveness has been verified by measurement results.

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“…In our Decap design, the channel length and the channel width of a single Decap cell is set to 700 and 968.75 nm, respectively, based on the design rules in [5]. The parameters of a conventional Decap that is required by a 20 2 20 m 2 area are shown in the column "Conv.…”

Section: A Basics Of Gdecapmentioning

confidence: 99%

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies

Chen

Roy

et al. 2009

IEEE Trans. VLSI Syst.

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To minimize the leakage power dissipation of present-day on-chip Decaps, we propose a gated decoupling capacitor (GDecap) technique that deactivates a Decap when it is not needed. The application of the proposed GDecap technique on an eight-way clock-gated clustered pipeline showed that on average, 41.7% Decap leakage power was reduced, with negligible ( 0 037%) worst-case performance degradation, at the 70-nm technology node. GDecap design incurred an area overhead of around 5.36% when compared with a conventional Decap design.

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Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance

Cited by 47 publications

References 8 publications

TSV Decoupling Schemes

TSV Decoupling Schemes

Low swing drivers based on charge redistribution

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies

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