System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

Wieferink, Andreas; Doerper, Malte; Leupers, Rainer; Ascheid, Gerd; Meyr, H.; Kogel, Tim; Braun, Gunnar; Nohl, Achim

doi:10.1049/ip-cdt:20045058

Cited by 23 publications

(7 citation statements)

References 3 publications

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“…Though some researchers [6] embed the ISS in the system simulator executable and eliminate the IPCs, the processor model does not become more accurate. The other kind of approaches [9][10] [11] uses the architecture description langrage (ADL) LISA [12] to make the system level description of processor architectures. The processors can be modeled on two major levels of abstraction: IA and CA models.…”

Section: Related Workmentioning

confidence: 99%

Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs

Wang

Shan

Liu

2012

2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery

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The increasing complexity of the current and future system-on-chip designs poses enormous challenges to systemlevel design. The uniform SystemC co-simulation methodology is proposed to describe the whole chip entirely with the same language. Elimination of the interaction between different simulators brings significant speedup in co-simulation. The processor model divides every instruction into a number of atomic operations, which makes it possible to accomplish fully cycle-accurate simulation. Meanwhile, the transaction-levelmodeling communication model enables each hardware block to be built at different abstraction levels. The methodology is demonstrated by the exemplary design of a MP3 decoding system.

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Section: Related Workmentioning

confidence: 99%

Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs

Wang

Shan

Liu

2012

2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery

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“…Kim et al (10) developed a new CDMA-based on-chip interconnection network using a Star NoC topology. To enable quick design of a multicore processor system and the evaluation of its interconnect system, Wieferink et al (11) developed a methodology for retargetable MPSoC integration at the system level based on LISA (12) processor models and the SystemC framework. (13) Single core applications utilize instruction level parallelism which is enabled by pipeline processors.…”

Section: Related Workmentioning

confidence: 99%

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Shee

Erdos

Parameswaran

2007

Int J Parallel Prog

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Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive realtime systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower * National ICT Australia is funded through the Australian Government's Backing Australia's Ability initiative, in part through the Australian Research Council. granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the masterslave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6× while with an area increase of only 3.1× (area increase to speedup ratio of just 0.68).

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“…To enable quick design of a multicore processor system and the evaluation of its interconnect system, Wieferink et. al [31] developed a methodology for retargetable MPSoC integration at the system level based on LISA [30] processor models and the SystemC [4] framework.…”

Section: Related Workmentioning

confidence: 99%

Design methodology for pipelined heterogeneous multiprocessor system

Shee

Parameswaran

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each of which make up a stage in a pipeline). We formulate the problem of mapping each algorithmic stage in the system to an ASIP configuration, and propose a heuristic to efficiently search the design space for a pipeline-based multi ASIP system.We have implemented the proposed heterogeneous multiprocessor methodology using a commercial extensible processor (Xtensa LX from Tensilica Inc.). We have evaluated our system by creating two benchmarks (MP3 and JPEG encoders) which are mapped to our proposed design platform. Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design. The minimum cost obtained through our heuristic was within 5.47% and 5.74% of the best possible values for JPEG and MP3 benchmarks respectively.

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System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

Cited by 23 publications

References 3 publications

Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs

Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Design methodology for pipelined heterogeneous multiprocessor system

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