Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Abstract

Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive realtime systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower * National ICT Australia is funded through the Australian Government's Backing Australia's Ability initiative, in part through the Australian Research Council. granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the masterslave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6× while with an area increase of only 3.1× (area increase to speedup ratio of just 0.68).

Dynamic partitioning‐based JPEG decompression on heterogeneous multicore architectures

“…Research on heterogeneous computing is receiving attention with high-performance computing. Shee et al [24] conducted a case study on JPEG encoders on application-specific instruction-set processors (ASIPs). They evaluated a master-slave model and a pipelined parallel programming model.…”

“…Research on heterogeneous computing is receiving attention in high performance computing. Shee et al [21] conducted a case study on JPEG encoders on Application Specific Instruction-set Processors (ASIPs). They evaluated two parallel programming patterns: master-slave and pipeline.…”

Heterogeneous processor pipeline for a product cipher application

“…The researchers at UNSW have mainly targeted on the development of heterogeneous pipeline architectures and on the methods of their design space exploration. They have used a JPEG compression algorithm on various MPSoC architectures as a case study, as in [2] and [3], and carried out extensive research on its performance and the process of the design, as in [4].…”

“…Next, the gains in performance achieved by the optimized multiple-processor pipeline systems, over the optimized single processor system, were calculated as in (3).…”

Bi-criteria Pipeline Mappings for Parallel Image Processing

“…The pixel and block-based approach is however useful for small pictures only. Recently, Sheel et al [11] consider a pipeline architecture where each stage presents a step in the JPEG encoding. The targeted architecture consists of Xtensa LX processors which run subprograms of the JPEG encoder program.…”