Design methodology for pipelined heterogeneous multiprocessor system

Abstract

Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each of which make up a stage in a pipeline). We formulate the problem of mapping each algorithmic stage in the system to an ASIP configuration, and propose a heuristic to efficiently search the design space for a pipeline-based multi ASIP system.We have implemented the proposed heterogeneous multiprocessor methodology using a commercial extensible processor (Xtensa LX from Tensilica Inc.). We have evaluated our system by creating two benchmarks (MP3 and JPEG encoders) which are mapped to our proposed design platform. Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design. The minimum cost obtained through our heuristic was within 5.47% and 5.74% of the best possible values for JPEG and MP3 benchmarks respectively.

Customized MPSoC synthesis for task sequence

“…We use a number of Tensilica LX2 [6] processor cores, enhanced with custom instructions as the MPSoC platform, which is similar to architectures used in [3], [5].…”

“…In terms of task mapping, Benoit et al [7] classify the policies to map tasks onto a fixed number of PEs into three categories: one-to-one mapping, where each task gets its own dedicated PE [3], [2], an interval-based policy, where only tasks that are contiguous in the task graph can be mapped on a single PE [5], and a fully general policy without restrictions [4]. In this work, we use the interval-based policy, on a variable number of PEs.…”

“…Thus several works propose algorithms that approximate an optimal solution: [5] proposes an iterative heuristic approach, [4] uses evolutionary algorithms, and [3] uses heuristic approach as well. On the other hand, [2] proposes an integer linear programming (ILP) formulation, assisted with safe heuristics, which guarantees an optimal solution.…”

“…MPSoC platforms consisting of extensible processor cores are an excellent match for streaming applications [2], [3]. These applications can be partitioned into multiple computeintensive kernels or tasks and represented in the form of an acyclic task graph.…”

“…Rather than focusing on fixed architectures with a given number of PEs [4], [5], or performing an one-to-one mapping of tasks to PEs [2], [3], we consider different number of PEs and interval-based mapping policy. Observing the design space for MP3 or MPEG-2 encoder shown in Figure 3, it should be obvious that fixing the number of PEs can easily miss the global optima.…”