Customized MPSoC synthesis for task sequence

Abstract

Abstract-Multiprocessor System-on-Chip (MPSoC) platforms have become increasingly popular for high-performance embedded applications. Each processing element (PE) on such platforms can be tuned to match the computational demands of the tasks executing on it, creating a heterogeneous multiprocessor system. Extensible processor cores, where the base instruction-set architecture can be augmented with application-specific custom instructions, have recently emerged as flexible building blocks for heterogeneous MPSoC platforms. However, the customization of the different PEs has to be carried out in a synergistic manner so as to create an optimal system. In this work, we propose a pseudopolynomial time algorithm to design the most resource-efficient customized MPSoC platform for mapping linear task graphs representing streaming applications, under deadline constraints. Experimental validation with MP3 encoder and MPEG-2 encoder applications confirms the efficiency of our approach.

Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures

“…At the opposite of our work, [20] did not consider custom instructions sharing. [19] consider the sharing of runtime reconfigurable fabric between processors for mapping different hardware components executing different custom instructions, However, we propose to share the hardware components between different processors to execute different custom instructions.…”

“…In [20], the authors propose a pseudo-polynomial time algorithm to explore the design space of Multi-Application Specific Instruction Processor (or M-ASIP). Their algorithm identifies the appropriate application-partitions and identifies custom instructions satisfying the area-performance trade-off.…”

“…In [20,19], the authors consider multiprocessor architectures but they did not consider coarse grain instruction sharing. We think, in the context of FPGA based hybrid architectures, coarse grain hardware accelerators are much more efficient in terms of efficiency and power than fine grain hardware accelerators due to communications overheads.…”

“…We think, in the context of FPGA based hybrid architectures, coarse grain hardware accelerators are much more efficient in terms of efficiency and power than fine grain hardware accelerators due to communications overheads. Moreover, in [20,19], the fine grained hardware accelerators are implemented on runtime reconfigurable hardware resources. However, the primary drawback of using runtime reconfiguration is the significant delay of reprogramming the hardware.…”

Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC

“…They develop an algorithm to select the ISEs to be mapped and to optimize the fabric sharing between cores leading to the best execution time. In [9], the authors propose a pseudo-polynomial time algorithm to explore the design space of Multi-Application Specific Instruction Processor (or M-ASIP). In their approach task mapping and custom instruction sets selection are separated in 2 different phases.…”