System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems

Abstract

The problem of determining bounds for application completion times running on generic systems comprised of single or multiple voltagefrequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-driven variability. The approach provides an exact solution for the system-level timing yield in single clock, single voltage (SSV) and VFI systems with an underlying tree-based topology, and a tight upper bound for generic, non-tree based topologies. The results show that: (a) timing yield for overall sourceto-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems; and (b) multiple VFI, latency-constrained systems can achieve 11-90% higher timing yield than their SSV counterparts. The results are proven formally and supported by experimental results on two embedded applications, namely software defined radio and MPEG2 encoder.

System-level throughput analysis for process variation aware multiple voltage-frequency island designs

“…Researchers have only recently started looking at process variation at the microarchitecture or system level. Marculescu and Garg [2006] analyze the effect of WID process variations on the execution latency of embedded systems implemented as both fully synchronous and multiple VFI designs. The proposed techniques, however, are only applicable to embedded systems specified as acyclic component graphs.…”

“…Based on the required performance, each PE could be an embedded processor, a custom digital implementation or an imported Intellectual Property (IP) component. We now examine two implementation alternatives for such systems-a fully synchronous design (henceforth referred to as an SSV design in keeping with the terminology introduced by Marculescu and Garg [2006]) with a single global clock that drives all the PEs, or a multiple VFI design in which each voltage-frequency island is controlled by an independent clock source. We note that for SSV designs, the PEs communicate using point-to-point synchronous links, while in the multiple VFI design case, links that cross clock domains communicate via mixed-clock FIFO interfaces [Chelcea and Nowick 2001] modified to support voltage level conversion.…”

“…Furthermore, for each benchmark, we vary the communication to computation ratio of the PEs, as defined in Equation (1), by setting α i = (0.1, 0.3, 0.5) for all i ∈ (1, n). Finally, we assume that the cycle times of the PEs are normally distributed with a 3σ of 20% of the mean [Marculescu and Garg 2006]. Table I shows the error between the mean and the 99% yield points of the throughput distributions for each of the benchmarks for different values of the computation to communication ratio.…”

Evaluating voltage islands in CMPs under process variations

“…Variable Voltage/Frequency Islands (VFI's) have been previously used by other researchers [7,18,19]. Marculescu et al [18] show that VFI-based latency-constrained systems are more likely to meet timing constraints than Single Clock, Single Frequency (SSV) based systems.…”

Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

“…Statistical timing analysis has become an important verification tool at circuit and system level design [3], and the study of system timing variability as a function of device and circuit variation is of considerable present interest [4]. To first order, signal propagation time is determined by CV /I .…”