System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS)

Wang, J.M.; Srinivas, B.; Ma, Dongsheng; Chen, Charlie Chung-Ping; Li, Jun

doi:10.1109/iccad.2005.1560161

Cited by 3 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many earlier works, such as Narendra et al [2004], Mukhopadhyay and Roy [2003], Rao et al [2004], and Wang et al [2005], have been proposed for full-chip statistical leakage analysis considering the process variations. When the process-induced 51:4 R. Shen et al variabilities are spatially correlated, the computational cost of the distribution of total leakage of the chip becomes quadratic -O(n 2 ), where n is number of gates as the variance of a gate has to be computed with respect to all correlated gates.…”

Section: Prior Workmentioning

confidence: 99%

Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems

Shen

Tan

Wang

et al. 2012

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

In this article, we present a new full-chip statistical leakage estimation considering the spatial correlation condition (strong or weak). The new algorithm can deliver linear time, O(N), time complexity, where N is the number of grids on chip. The proposed algorithm adopts a set of uncorrelated virtual variables over grid cells to represent the original physical random variables and the cell size is determined by the spatial correlation length. In this way, each physical variable is always represented by virtual variables locally. We prove the number of neighbor cells for each grid cell is not related to the condition of spatial correlation (from no correlation to 100% correlated), which leads to linear time complexity in terms of number of gates. We compute the gate leakage by the orthogonal polynomials-based collocation method. The total leakage of a whole chip can be computed by simply summing up the coefficients of corresponding orthogonal polynomials in each grid cell. Furthermore, we develop a look-up table to cache statistical information for each type of gate instead of calculating leakage for every single instance of gate on a chip. As a result, a new statistical leakage characterization in Standard Cell Library (SCL) is put forward. Furthermore, an incremental analysis algorithm is proposed to update the chip-level statistical leakage information efficiently after a few changes are made. The proposed method has no restrictions on static leakage models, or types of leakage distributions. The large circuit examples in 45nm CMOS process demonstrate the proposed algorithm is 1000X faster than a recently proposed grid-based method with similar accuracy and many orders of magnitude times speedup over the Monte Carlo method. Experimental results also show the incremental analysis provides about 10X further speedup. We expect the incremental analysis could achieve more speedup over the full leakage analysis for larger problem sizes.

show abstract