System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures

Schliecker, Simon; Rox, Jonas; Negrean, Mircea; Richter, Kai; Jersak, Marek; Ernst, Rolf

doi:10.1109/tcad.2009.2013286

Cited by 42 publications

(18 citation statements)

References 34 publications

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“…Performance evaluation of distributed architectures in the automotive domain calls for specific evaluation methods. In [5], various analysis approaches are described for timing estimation in networked architectures. Three distinguishable approaches are identified: classical real-time system theory, timed automatas, and simulation.…”

Section: Related Workmentioning

confidence: 99%

Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach

Majdoub

Nours

Pasquier

et al. 2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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Due to increasing complexity of communication infrastructures in the automotive domain, reliable models are necessary in order to assist designers in the development process of networked embedded systems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the application of a specific modeling approach for performance evaluation of a networked embedded system inspired from the automotive domain. The considered approach is illustrated by the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. The created model incorporates description of various communication layers and simulation of the model allows evaluation of time properties and memory cost inferred.

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Section: Related Workmentioning

confidence: 99%

Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach

Majdoub

Nours

Pasquier

et al. 2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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show abstract

“…another task finishing or data arriving over a bus. This problem is addressed by embedding the analysis into a compositional analysis approach such as [17] and [20], where task activating event models are provided and iteratively refined during the analysis procedure. The analysis of the shared resource bounds and the above response time analysis then need to be repeated as well, until the definite event models have been found.…”

Section: Multiprocessor Response Time Analysismentioning

confidence: 99%

Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources

Negrean

Schliecker

Ernst

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-As multiprocessor systems are increasingly used in real-time environments, scheduling and synchronization analysis of these platforms receive growing attention. However, most known schedulability tests lack a general applicability. Common constraints are a periodic or sporadic task activation pattern, with deadlines no larger than the period, or no support for shared resource arbitration, which is frequently required for embedded systems. In this paper, we address these constraints and present a general analysis which allows the calculation of response times for fixed priority task sets with arbitrary activations and deadlines in a partitioned multiprocessor system with shared resources. Furthermore, we derive an improved bound on the blocking time in this setup for the case where the shared resources are protected according to the Multiprocessor Priority Ceiling Protocol (MPCP).

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“…The worst-case execution time (WCET) of that application has to be less than or equal to this upper bound to achieve predictability. As application demands continue to increase from the avionics [3] and automotive [4] domains, there is a surge in wanting to use multi-core platforms for their deployments. This is primarily due to the benefits multi-core platforms provide in cost, and performance.…”

Section: Introductionmentioning

confidence: 99%

Predictable Cache Coherence for Multi-core Real-Time Systems

Hassan

Kaushik

Patel

2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We accomplish this by proposing a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on predictable MSI (PMSI) protocol. Our analysis shows that while the arbitration latency scales linearly, the coherence latency scales quadratically with the number of cores. We implement PMSI in gem5, and execute SPLASH-2 and synthetic multi-threaded workloads. Our empirical results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves average-case performance by up to 4× over the next best predictable alternative. PMSI has average slowdowns of 1.45× and 1.46× compared to conventional MSI and MESI protocols, respectively.

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System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures

Cited by 42 publications

References 34 publications

Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach

Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach

Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources

Predictable Cache Coherence for Multi-core Real-Time Systems

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