Predictable Cache Coherence for Multi-core Real-Time Systems

Abstract

Abstract-This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We accomplish this by proposing a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on predictable MSI (PMSI) protocol. Our analysis shows that while the arbitration latency scales linearly, the coherence latency scales quadratically with the number of cores. We implement PMSI in gem5, and execute SPLASH-2 and synthetic multi-threaded workloads. Our empirical results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves average-case performance by up to 4× over the next best predictable alternative. PMSI has average slowdowns of 1.45× and 1.46× compared to conventional MSI and MESI protocols, respectively.

Developing a Multicore Platform Utilizing Open RISC-V Cores

“…Meanwhile, when applying TC, programmers must take into account real-time computing, reliability, and power/energy consumption resulting from cache usage. More precisely, the use of cache in shared data can cause cache interference issues between tasks, which can significantly hamper the predictability and analysis of multicore real-time systems [14], [15]. Recent studies on cache architecture and cache coherence show that they have a significant impact on system reliability [16], [17].…”

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

“…Hassan et al [34] proposed PMSI, which is a predictable cache coherence protocol for multi-core systems. PMSI is the extended version of the classic MSI protocol and improved it with transient coherence states to bound the worst-case access latency.…”

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

“…The scope of this survey is restricted to timing verification techniques for multi-core and manycore platforms that specifically consider the impact of shared hardware resources. The following areas of related research are outside of the scope of this survey: (i) works that introduce isolation mechanisms for multi-core systems, but rely on existing analysis for timing verification (examples include the work on the MERASA [94] and T-CREST projects [111], as well as work on shared cache management techniques (surveyed in [46]) and cache coherence [47,56]; (ii) works that introduce mechanisms and analyses of the worst-case latencies for a particular component, for example predictable DDR-DRAM memory controllers 4 (comparative studies in [49,57]), but rely on these latencies being incorporated into existing analyses for timing verification; (iii) scheduling and schedulability analyses for multiprocessor systems that consider only a simple abstract model of task execution times (surveyed in [38]); (iv) multiprocessor software resource sharing protocols; (v) timing verification techniques for many-core systems with a Network-on-Chip (NoC) (surveyed in [59,70]) which consider only the scheduling of the NoC, or consider that tasks on each core execute out of local memory with the only interaction with packet flows being through a consideration of release jitter; (vi) measurement-based and measurement-based probabilistic timing analysis methods; (vii) research that focuses on timing verification of single-core systems. Further, the survey does not cover specific research into multi-cores with GPGPUs or re-configurable hardware.…”