Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Aghilinasab, Homa; Ali, Waqar; Yun, Heechul; Pellizzoni, Rodolfo

doi:10.1109/tcad.2020.3012210

Cited by 12 publications

(6 citation statements)

References 58 publications

(75 reference statements)

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“…It significantly reduces the latency of memory allocation and deallocation by adjusting the focus of concurrent response or resource aggregation based on different memory request patterns to adapt to concurrency pressure. Aghilinasab et al [18] studied memory-intensive applications in real-time and mixed-criticality systems and proposed a scheme to adjust memory bandwidth allocation by dynamically monitoring application progress. Its effectiveness was demonstrated through benchmark testing.…”

Section: Related Workmentioning

confidence: 99%

Memory Allocation Strategy in Edge Programmable Logic Controllers Based on Dynamic Programming and Fixed-Size Allocation

Cheng,

Wan,

Ding

et al. 2023

Applied Sciences

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With the explosive growth of data at the edge in the Industrial Internet of Things (IIoT), edge devices are increasingly performing more data processing tasks to alleviate the load on cloud servers. To achieve this goal, Programmable Logic Controllers (PLCs) are gradually transitioning into edge PLCs. However, efficiently executing a large number of computational tasks in memory-limited edge PLCs is a significant challenge. Therefore, there is a need to design an efficient memory allocation strategy for edge PLCs. This paper proposes a dynamic memory allocation strategy for edge PLCs. It adopts an approach of organizing memory into small blocks to handle memory requests from real-time tasks and utilizes a well-performing dynamic programming method for resource allocation problems to handle memory requests from non-real-time tasks. This approach ensures real-time performance while improving the efficiency of non-real-time task processing. In the simulation experiments, the algorithm implemented based on this allocation strategy is compared with the default method and several open-source memory allocators. The experimental results demonstrate that the proposed algorithm, on average, improves the speed of real-time task processing by 13.7% and achieves a maximum speed improvement of 17.0% for non-real-time task processing. The experimental results show that the allocation strategy effectively improves memory allocation efficiency in memory-limited environments.

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Section: Related Workmentioning

confidence: 99%

Memory Allocation Strategy in Edge Programmable Logic Controllers Based on Dynamic Programming and Fixed-Size Allocation

Cheng,

Wan,

Ding

et al. 2023

Applied Sciences

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“…Sohal et al [4] implemented a framework for analyzing the memory demand and to predict the timing of real-time workloads on CPUs and hardware accelerators. Several memory-bandwidth regulations mechanisms have been proposed also for hardware accelerators, such as GPUs or FPGAs [8]- [10]. Several techniques have been also proposed to improve predictability of cache memories: the interested reader can refer to the survey by Gracioli et al [30].…”

Section: Related Workmentioning

confidence: 99%

“…The real-time systems research community is studying this problem since almost a decade, proposing many clever solutions to improve the memory access predictability of different types of memories and shared buses, both when accessed by CPU cores [2]- [4], I/O devices [5]- [7], and hardware accelerators [8]- [10]. These solutions include the usage of performance counters to keep track of the number of memory accesses [2], the development of memory-aware execution models [11,12], and the design and implementation of custom components as predictable buses [7,13] and memory controllers [14]- [16].…”

Section: Introductionmentioning

confidence: 99%

Analyzing Arm's MPAM From the Perspective of Time Predictability

Zini

Casini

Biondi

2023

IEEE Trans. Comput.

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With heterogeneous multi-core platforms being crucial to execute the highly demanding workloads of modern applications, memory-access predictability remains a key issue for the system's safety. Many solutions have been proposed over the years, but none has been applied on a large scale. Nowadays, we are in front of an unprecedented opportunity to have an impact on commercial platforms: the Memory System Resource Partitioning and Monitoring (MPAM) specification by Arm, which describes different memory-access regulation mechanisms, presenting a valuable industrial attempt to address this issue. However, several points of the specification are described at a high level only, leaving plenty of room for interpretation to hardware manufacturers. This paper takes a close look at the memory-access regulation mechanisms in the MPAM specification and provides some detailed instantiations of such mechanisms. A fine-grained memory contention analysis is presented for each of them to finally enable a comparison of their worst-case performance.

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“…Very recently, Sohal et al 31 proposed the Envelope‐aWare Predictive model, a framework that allows analyzing the memory demand of applications and making predictions on the timing behavior of workloads running on CPUs and accelerators. Similar mechanisms have been implemented to realize memory access regulation in the context of hardware accelerators 3,32‐34 . Very recently, Serrano‐Cases et al 35 studied the behavior of the QoS‐400 regulators on the Ultrascale+, but without covering I/O traffic and considering a bare‐metal use case.…”

Section: Related Workmentioning

confidence: 99%

“…Similar mechanisms have been implemented to realize memory access regulation in the context of hardware accelerators. 3,[32][33][34] Very recently, Serrano-Cases et al 35 studied the behavior of the QoS-400 regulators on the Ultrascale+, but without covering I/O traffic and considering a bare-metal use case. Several techniques have also been proposed to improve the predictability and to analyze caches: [36][37][38] the survey by Gracioli et al 5 presents a good summary of such techniques.…”

Section: Related Workmentioning

confidence: 99%

Profiling and controlling I/O‐related memory contention in COTS heterogeneous platforms

et al. 2021

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Motivated by the increasing number of embedded applications that make use of traffic-intensive I/O devices, this work studies the memory contention generated by I/O devices and investigates on the regulation of the bus traffic they generate by means of COTS regulators, namely the QoS-400 by Arm. To this purpose, the behavior of the QoS-400 regulators is analytically characterized and then, taking the Xilinx Ultrascale+ as a reference modern heterogeneous platform, a software infrastructure to control such regulators from Linux is proposed. As an experience report, this article presents the results of an extensive experimental evaluation, based on both benchmarks and microbenchmarks, aimed at validating the effectiveness of QoS-400 regulators in predictably controlling I/O-related memory traffic, as well as assessing the impact of the regulation on software applications and I/O devices themselves.

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Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Abstract: This thesis consists of material all of which I authored or co-authored: see Statement of Contributions included in the thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners.

Cited by 12 publications

References 58 publications

Memory Allocation Strategy in Edge Programmable Logic Controllers Based on Dynamic Programming and Fixed-Size Allocation

Memory Allocation Strategy in Edge Programmable Logic Controllers Based on Dynamic Programming and Fixed-Size Allocation

Analyzing Arm's MPAM From the Perspective of Time Predictability

Profiling and controlling I/O‐related memory contention in COTS heterogeneous platforms

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