Profiling and controlling I/O‐related memory contention in COTS heterogeneous platforms

Zini, Matteo; Cicero, Giorgiomaria; Casini, Daniel; Biondi, Alessandro

doi:10.1002/spe.3053

Cited by 10 publications

(6 citation statements)

References 59 publications

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“…Unfortunately, the authors discovered that these technologies could be used to launch new and powerful attacks. Borgioli et al [49] proposed an I/O virtualization mechanism resilient to denial-of-service (DoS) attacks due to I/O-related memory traffic, leveraging the QoS-400 regulators by Arm [50].…”

Section: Related Workmentioning

confidence: 99%

Maximizing the Security Level of Real-Time Software While Preserving Temporal Constraints

et al. 2023

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Embedded computing systems are becoming increasingly relevant in the Internet of Things (IoT) and edge computing domains, where they are often employed as the control entity of a cyber-physical system. When operating in such interconnected domains, a software system is susceptible to cyber-attacks from external agents, which can compromise the correct behavior of the system. In addition, the software executing in these systems is typically characterized by stringent timing constraints, which must be satisfied during system execution. Enabling software protections to enhance the security level of the embedded software comes at the cost of increasing the computation times of the tasks, introducing the risk of deadline misses that could also jeopardize the system behavior. This paper presents a methodology to optimize the security level of real-time software while preserving system-wide schedulability by leveraging timing analysis. The proposed approach is based on a mixed-integer linear programming (MILP) formulation that maximizes the security level of the tasks and integrates a response-time analysis technique to assess the schedulability of the system whenever additional protections are activated to shield the software against cyber-attacks targeting specific classes of vulnerabilities. An experimental evaluation is presented to assess the performance of the proposed approach on a representative set of tasks included in standard benchmarking suites for embedded software.

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Section: Related Workmentioning

confidence: 99%

Maximizing the Security Level of Real-Time Software While Preserving Temporal Constraints

et al. 2023

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“…In the experiments where QoS regulation is considered, we varied the average rate configuration parameter of the QoS-400 since it is the only one responsible for the long-term behavior of the device when it is subject to a heavy traffic load [11]. Therefore, different QoS configurations correspond to a different average number of transactions per time unit emitted by the Ethernet device.…”

Section: A Experimental Setupmentioning

confidence: 99%

“…The management of I/O devices is also crucial for reducing the delays due to memory contention when cores and I/O devices simultaneously access a globally-shared memory (usually, a DDR memory). To limit the lateness that the memory traffic might introduce during I/O operations, some platforms (e.g., the Xilinx Zynq Ultrascale+ MPSoC [9]) are equipped with hardware regulators capable of controlling the number of memory transactions allowed from each device in a given time interval [10,11], thus introducing a reservation mechanism to control the I/O-related memory traffic.…”

Section: Introductionmentioning

confidence: 99%

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An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems

Borgioli

Zini

Casini

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Modern applications are often characterized by a tight interaction with I/O devices. At the same time, many application domains are also facing a shift towards an integrated approach where multiple applications with mixed levels of safety and security need to co-exist on top of a shared hardware platform, which is typically managed by a hypervisor. This gives rise to the need for a predictable mechanism allowing multiple virtual machines to share I/O devices, while at the same time controlling contention delays when they access global memory.To deal with these shortcomings, this paper proposes an I/O virtualization framework providing support for controlling the I/O-related memory contention by leveraging the ARM QoS-400 regulators. Extensive experiments are performed to compare the proposed solution with the Xen hypervisor, showing improvements up to 8x when controlling the I/O-related memory contention.

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“…The real-time systems research community is studying this problem since almost a decade, proposing many clever solutions to improve the memory access predictability of different types of memories and shared buses, both when accessed by CPU cores [2]- [4], I/O devices [5]- [7], and hardware accelerators [8]- [10]. These solutions include the usage of performance counters to keep track of the number of memory accesses [2], the development of memory-aware execution models [11,12], and the design and implementation of custom components as predictable buses [7,13] and memory controllers [14]- [16].…”

Section: Introductionmentioning

confidence: 99%

Analyzing Arm's MPAM From the Perspective of Time Predictability

Zini

Casini

Biondi

2023

IEEE Trans. Comput.

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With heterogeneous multi-core platforms being crucial to execute the highly demanding workloads of modern applications, memory-access predictability remains a key issue for the system's safety. Many solutions have been proposed over the years, but none has been applied on a large scale. Nowadays, we are in front of an unprecedented opportunity to have an impact on commercial platforms: the Memory System Resource Partitioning and Monitoring (MPAM) specification by Arm, which describes different memory-access regulation mechanisms, presenting a valuable industrial attempt to address this issue. However, several points of the specification are described at a high level only, leaving plenty of room for interpretation to hardware manufacturers. This paper takes a close look at the memory-access regulation mechanisms in the MPAM specification and provides some detailed instantiations of such mechanisms. A fine-grained memory contention analysis is presented for each of them to finally enable a comparison of their worst-case performance.

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Profiling and controlling I/O‐related memory contention in COTS heterogeneous platforms

Cited by 10 publications

References 59 publications

Maximizing the Security Level of Real-Time Software While Preserving Temporal Constraints

Maximizing the Security Level of Real-Time Software While Preserving Temporal Constraints

An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems

Analyzing Arm's MPAM From the Perspective of Time Predictability

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