Analyzing Arm's MPAM From the Perspective of Time Predictability

Abstract

With heterogeneous multi-core platforms being crucial to execute the highly demanding workloads of modern applications, memory-access predictability remains a key issue for the system's safety. Many solutions have been proposed over the years, but none has been applied on a large scale. Nowadays, we are in front of an unprecedented opportunity to have an impact on commercial platforms: the Memory System Resource Partitioning and Monitoring (MPAM) specification by Arm, which describes different memory-access regulation mechanisms, presenting a valuable industrial attempt to address this issue. However, several points of the specification are described at a high level only, leaving plenty of room for interpretation to hardware manufacturers. This paper takes a close look at the memory-access regulation mechanisms in the MPAM specification and provides some detailed instantiations of such mechanisms. A fine-grained memory contention analysis is presented for each of them to finally enable a comparison of their worst-case performance.

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

“…Architecture-level features such as Arm's MPAM (ARM 2022a) or Intel's RDT (Intel 2024) aim to deliver improved (QoS) control over the memory subsystem. Real-time characteristics of RDT are analyzed by Sohal et al (2022) and a theoretical analysis of MPAM characteristics is presented by Zini et al (2023). Unfortunately, the availability of such architectural-level features on current systems is still very limited.…”