System-level energy estimation with Powersim

Giammarini, Marco; Conti, Massimo; Orcioni, Simone

doi:10.1109/icecs.2011.6122376

Cited by 18 publications

(11 citation statements)

References 8 publications

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“…Lebreton and Vivet (2008) adopt this methodology in designs that have voltage scaling. Giammarini et al (2011) propose a tool called PowerSim on the same lines. This tool uses extensive energy models that are collected using empirical measurements on embedded micro-controllers.…”

Section: Kernel Based Approachesmentioning

confidence: 99%

Processor power estimation techniques: a survey

Sultan¹,

Ananthanarayanan²,

Sarangi³

2014

IJHPSA

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Since the end of the nineties, power dissipation has been regarded as a first order design constraint in processors. Increased power dissipation along with the resultant rise in die temperature is considered as the single largest bottleneck for increasing processor frequency and complexity. Consequently, it is very important from both a technical as well as commercial perspective to accurately estimate processor power such that designers can tailor their architecture, software and systems to minimize power consumption. In this paper, we provide a survey of most of the processor specific power estimation techniques proposed after the mid nineties. In specific, we look at estimating power both at design time as well as runtime. The former approach is more suitable for early stage architectural exploration, and the latter approach is more germane to creating power efficient application software. We broadly focus on estimating power using system level models, architectural simulation, hardware performance counters, on-chip temperature profiles, and program execution profiles. We showcase a broad range of methods for power estimation using simulators, compilers, profilers, and sophisticated mathematical analysis routines.

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Section: Kernel Based Approachesmentioning

confidence: 99%

Processor power estimation techniques: a survey

Sultan¹,

Ananthanarayanan²,

Sarangi³

2014

IJHPSA

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show abstract

“…Generally, the simulation time in this group is long while the accuracy is high. Powersim [13], an example of an instruction-based power model, presents a C++ library that monitors a limited set of SystemC operators and applies an energy model to the monitored operations. A functional level power analysis approach is used in PETS [14].…”

Section: Related Workmentioning

confidence: 99%

Automated estimation of power consumption for rapid system level design

Samei

Dömer

2014

2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)

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This paper describes an early power estimation method for Electronic System Level(ESL) design, which provides a scalable API to support automated power profiling and analysis at the early stages of the design process. The proposed framework utilizes a high-level power modeling mechanism along with an automated profiler to extract energy activity from the simulated system model. These two features are integrated into PowerMeter, a framework that automatically annotates power meters as well as energy and performance functions into the executable model. This integrated profiling helps the designer to rapidly explore the design space, trading off performance against power cost in order to make best design decisions. Our approach also provides the designer with the ability to quantify the effect of revisions in the ESL design models, in terms of both power and performance. Despite the high abstraction level, our results show that the PowerMeter delivers rapid estimates with high fidelity and at minimal cost.

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“…In comparison with this work, it uses a strategy based on logging the execution of special modules and signals extended from regular SystemC ones, instead of a probability model, as presented here. In [15] a SystemC class library is proposed to the calculate the energy consumption of hardware described with SystemC TLM, and the power model was based on experimental results performed in laboratory, while approach of the presented work is based on the translation of modules from VHDL to SystemC RTL and on probability models. Further works concern the extension of the approach also to TLM.…”

Section: Related Workmentioning

confidence: 99%

Modeling and Implementation of a Power Estimation Methodology for SystemC

Kuehnle¹,

Wagner²,

Brito

et al. 2012

International Journal of Reconfigurable Computing

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This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces so that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of the underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis flow using PPR simulation, based on Xilinx technology.

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System-level energy estimation with Powersim

Cited by 18 publications

References 8 publications

Processor power estimation techniques: a survey

Processor power estimation techniques: a survey

Automated estimation of power consumption for rapid system level design

Modeling and Implementation of a Power Estimation Methodology for SystemC

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