Modeling and Implementation of a Power Estimation Methodology for SystemC

Kuehnle, M.; Wagner, A.; Brito, Alisson V.; Becker, Juergen

doi:10.1155/2012/439727

Cited by 3 publications

(2 citation statements)

References 11 publications

(10 reference statements)

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“…However, these procedures require high memory and time for calculating logic values when the number of inputs and nodes in the circuit increase. Kuehnle, Wagner, Brito, and Becker in [9] presented a mathematical model for estimating power. They integrated the model in a tool to translate the system described in VHDL language to SystemC.…”

Section: A Techniques Of Power Estimationmentioning

confidence: 99%

Teaching low-power design with an FPGA-based hands-on and remote lab

AbuShanab

Winzker

Brück

2015

2015 IEEE Global Engineering Education Conference (EDUCON)

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This paper describes a project carried out at the Bonn-Rhein-Sieg University to teach low-power digital design structures in a laboratory. Low-power design has become one of the most essential constraints in digital systems, especially in portable devices. For this purpose, low-power design is a topic addressed in electrical and computer curricula, but it also requires applications in a laboratory. Therefore, this project focuses on preparing students for current trends in low-power design by examining realistic applications of its basic theories and principles, either hands-on or remotely. The laboratory's experiments use a field programmable gate array (FPGA) as a design platform for implementing the students' digital designs. This contribution reports on our first experiences in teaching low-power design in the lab. This paper focuses on the educational impact on students regarding the following: (1) overall objectives in the laboratory, (2) experimental exercises with low-power techniques, and (3) using educational FPGA boards and the EduPow board. The EduPow board is a developed hands-on board at the Bonn-Rhein-SiegUniversity that is relatively specific on using various signal image-processing applications to directly observe the power dissipation of a student's digital algorithm. Our assessment of the low-power design lab shows that the requirements and objectives of this project are fairly well satisfied. In addition, students' feedback indicates that using the EduPow board is more attractive and motivational in their work.

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Section: A Techniques Of Power Estimationmentioning

confidence: 99%

Teaching low-power design with an FPGA-based hands-on and remote lab

AbuShanab

Winzker

Brück

2015

2015 IEEE Global Engineering Education Conference (EDUCON)

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“…In this context, power consumption estimation at the system level (ESL) has become an important research topic in recent years. Many of the methodologies focus on the relationship between power estimation accuracy and its computational cost at ESL level [2] [5] [6] [11].…”

Section: Introductionmentioning

confidence: 99%

An Approach for Power Estimation at Electronic System Level using Distributed Simulation

Oliveira¹,

Brito²,

Araújo³

et al. 2020

JICS

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The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

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Processor power estimation techniques: a survey

Sultan¹,

Ananthanarayanan²,

Sarangi³

2014

IJHPSA

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Since the end of the nineties, power dissipation has been regarded as a first order design constraint in processors. Increased power dissipation along with the resultant rise in die temperature is considered as the single largest bottleneck for increasing processor frequency and complexity. Consequently, it is very important from both a technical as well as commercial perspective to accurately estimate processor power such that designers can tailor their architecture, software and systems to minimize power consumption. In this paper, we provide a survey of most of the processor specific power estimation techniques proposed after the mid nineties. In specific, we look at estimating power both at design time as well as runtime. The former approach is more suitable for early stage architectural exploration, and the latter approach is more germane to creating power efficient application software. We broadly focus on estimating power using system level models, architectural simulation, hardware performance counters, on-chip temperature profiles, and program execution profiles. We showcase a broad range of methods for power estimation using simulators, compilers, profilers, and sophisticated mathematical analysis routines.

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Modeling and Implementation of a Power Estimation Methodology for SystemC

Cited by 3 publications

References 11 publications

Teaching low-power design with an FPGA-based hands-on and remote lab

Teaching low-power design with an FPGA-based hands-on and remote lab

An Approach for Power Estimation at Electronic System Level using Distributed Simulation

Processor power estimation techniques: a survey

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