System-level design of a delta-sigma modulator target for next generation wireless application

Abstract

Delta-sigma (∆Σ) converters have been widely used in wireless communications as they provide the most economic speed-accuracy tradeoff. This paper presents the system-level design of a multi-bit continuous-time (CT) ∆Σ analog-to-digital converter (ADC) targeting for the next generation wireless application. The modulator topology is determined based on the application requirements using MATLAB software. The nonidealities associated with the multi-bit CT ∆Σ modulator, such as excess loop delay, system clock jitter, integrator nonideality and multi-bit digital-toanalog converter (DAC) element mismatch, are also modeled in the system-level. With all the nonidealities included, the designed modulator achieves a dynamic range (DR) of 74dB (12 bits) in a 50-MHz signal bandwidth.Index Terms -Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma (∆Σ) modulation, multibit, system-level.

System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications

“…Feedback topologies are less suitable for low-voltage, deep submicron technology implementation due to the large signal swing at the output of the first stage integrator opamp [6]. Whereas, the main advantages of feed-forward architecture is that the cascaded integrators handle only a part of the input signal, therefore, the integrators can have a relaxed dynamic range and scaling requirements.…”