System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications

Abstract

This paper reports the system-level design of a reconfigurable continuous-time sigma-delta modulator that is capable to perform the analog-to-digital conversion for GSM, LTE5 and WLAN wireless standards. The modulator architecture consists of a third-order loop filter using feed-forward summation topology and a 4-bit internal quantizer. The modulator coefficients were directly synthesized in the continuoustime domain which provides a more efficient modulator in terms of noise shaping, efficiently placing the zeros and poles of the noise transfer function. The reconfiguration strategy is performed at the circuit-level by using digital signals that selects the appropriate transconductances, capacitors and the sampling frequency for each standard. SIMULINK building blocks that model the non-idealities associated with the modulator were employed in the system-level simulations. The results show that the modulator achieves a signal-to-noise plus distortion ratio of 96/83/81 dB within a 0.2/5/10 MHz signal bandwidth.