Synthetic circuit generation using clustering and iteration

Abstract

The development of next-generation CAD tools and FPGA architectures require benchmark circuits to experiment with new algorithms and architectures. There has always been a shortage of good public benchmarks for these purposes, and even companies that have access to proprietary customer designs could benefit from designs that meet size and other particular specifications. In this paper, we present a new method of generating realistic synthetic benchmark circuits to help alleviate this shortage.The method significantly improves the quality of previous work by imposing a hierarchy of circuits through clustering and by using a simpler method of characterizing the nature of sequential circuits. Also, in contrast to current constructive generation methods [7][8][9][11][12][13][14][15][16]18,19], we employ new iterative techniques in the generation that provide better control over the generated circuit's characteristics. As in previous work, we assess the realism of the generated circuits by comparing properties of real circuits and generated "clones" of the real circuit after placement and routing. On average, the real and clone circuits' total detailed wirelength differ by only 14%, a major improvement over previous results. In addition, the minimum track count is within 14% and the critical path delay is within 10%.

Evolution of synthetic RTL benchmark circuits with predefined testability

“…Pistorius et al [1999], and later Verplaetse et al [2002] and Stroobandt et al [2000], created tools for generating synthetic benchmark circuits for partitioning-algorithms testing. Hutton et al [2002] and Kundarewich and Rose [2004] have developed a tool for the design of sequential benchmark circuits by cloning existing circuits. The cloned circuits have been used for testing partitioning and place-and-route algorithms.…”

“…Synthetic benchmark circuits have been recognized as a viable alternative to the standard benchmark circuits (e.g., Darnauer and Dai [1996], Iwama et al [1997], Pistorius et al [1999], Verplaetse et al [2002], Hutton et al [2002], and Kundarewich and Rose [2004]). They are usually created by an automated procedure and constrained to have a specific set of desirable characteristics (e.g., size, topology, testability, and function).…”

Perturb+mutate

“…In Hutton et al [2002], the tools are extended to include sequential circuits. Refinements to improve the reproduction of locality were introduced in the CCirc and CGen tools [Kundarewich and Rose 2004]. CCirc first partitions a circuit and characterizes the partitions separately, then CGen generates clusters accordingly and joins them together.…”

“…Perturbing is based on edge-swapping, a technique that has been used in several prior efforts [Ghosh et al 1998;Coudert et al 2000, Kundarewich andRose 2004]. However, an important feature unique to our Perturb tool is ancestor depth control (ADC), a method used to preserve circuit locality during swapping.…”

“…However, an important feature unique to our Perturb tool is ancestor depth control (ADC), a method used to preserve circuit locality during swapping. Ancestor depth control results in a clone circuit that reproduces the postrouting properties (channel width, wirelength, and criticalpath delay) of the original circuit as well as CGen [Kundarewich and Rose 2004], the best generator known to-date.…”