Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties

Pecenka, T.; Kotásek, Zdenĕk; Sekanina, Lukáš; Strnadel, Josef

doi:10.1109/eh.2005.10

Cited by 13 publications

(12 citation statements)

References 12 publications

(10 reference statements)

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“…The TA presented method presented in the paper was primary developed for utilization in Cirgen [11]. Cirgen is a software tool which allows developing RTL circuits with testability parameters predefined by a user.…”

Section: Application Of Developed Ta Methodsmentioning

confidence: 99%

“…Originally, the methodology was supposed to be used for fast testability estimation in software tool utilizing evolutionary techniques to design a circuit with predefined structural and diagnostic properties [8,11]. Anyway, it can be stated that the developed methodology can be used not only in the above mentioned software tool but also in any other methodology the goal of which is to estimate testability of a circuit described as an RTL structure.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Testability Estimation Based on Controllability and Observability Parameters

Pecenka

Strnadel

Kotásek

et al. 2006

9th EUROMICRO Conference on Digital System Design (DSD'06)

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In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The resultsgained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

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Section: Application Of Developed Ta Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Testability Estimation Based on Controllability and Observability Parameters

Pecenka

Strnadel

Kotásek

et al. 2006

9th EUROMICRO Conference on Digital System Design (DSD'06)

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“…Fault tolerance [89], fault detection and repair [90][91][92], although already a focus in EH provide many opportunities for further discoveries. Moving from faults to testinga significant challenge facing the electronic industry, provides many opportunities such as in test generation [93] and testing methodology benchmark circuits [94,95]. Surprisingly, although a major focus within the electronic industry, power usage [96] is only recently gaining attention in the EH field.…”

Section: Applicationsmentioning

confidence: 99%

Challenges of evolvable hardware: past, present and the path to a promising future

Haddow

Tyrrell

2011

Genet Program Evolvable Mach

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Nature is phenomenal. The achievements in, for example, evolution are everywhere to be seen: complexity, resilience, inventive solutions and beauty. Evolvable Hardware (EH) is a field of evolutionary computation (EC) that focuses on the embodiment of evolution in a physical media. If EH could achieve even a small step in natural evolution's achievements, it would be a significant step for hardware designers. Before the field of EH began, EC had already shown artificial evolution to be a highly competitive problem solver. EH thus started off as a new and exciting field with much promise. It seemed only a matter of time before researchers would find ways to convert such techniques into hardware problem solvers and further refine the techniques to achieve systems that were competitive with or better than human designs. However, 15 years on-it appears that problems solved by EH are only of the size and complexity of that achievable in EC 15 years ago and seldom compete with traditional designs. A critical review of the field is presented. Whilst highlighting some of the successes, it also considers why the field is far from reaching these goals. The paper further redefines the field and speculates where the field should go in the next 10 years.

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“…In these applications (for example, in signal processing [26]), the evolutionary design is performed using a training set and the solution is validated using a test set. In some other cases it is sufficient to evaluate only some structural properties of candidate circuits which can be done with linear or quadratic time complexity (with respect to the number of circuits elements) even for complex circuits [18]. Then, relatively complex circuits can be evolved.…”

Section: Fitness Calculation As a Bottleneckmentioning

confidence: 99%

“…Fortunately, some methods exist to predict testability of a digital circuit in a quadratic time [18]. Hence, EA was utilized to design benchmark circuits with the required testability properties [18].…”

Section: Evolution Of Benchmark Circuitsmentioning

confidence: 99%

Evolutionary Design of Digital Circuits: Where Are Current Limits?

Sekanina

2006

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

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The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these approaches. In particular, gate-level evolution, circuit evolution in PLAs, functional-level evolution, incremental evolution, evolution utilizing developmental schemes and some application-specific schemes are analyzed. It is shown that we are able to effectively explore the search spaces not much larger than 2 1000 points and that the innovative solutions can be produced independently of the utilized method.

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Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties

Abstract: Abstract

Cited by 13 publications

References 12 publications

Testability Estimation Based on Controllability and Observability Parameters

Testability Estimation Based on Controllability and Observability Parameters

Challenges of evolvable hardware: past, present and the path to a promising future

Evolutionary Design of Digital Circuits: Where Are Current Limits?

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