Synthesis of carry select adder in 65 nm FPGA

Yousuf, Romana; Najeeb-ud-Din,

doi:10.1109/tencon.2008.4766397

Cited by 9 publications

(6 citation statements)

References 10 publications

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“…viz. CSLA-CLA, CSLA BEC-CLA, CSLA-SCBCLA, and CSLA BEC-SCBCLA were described topologically in Verilog HDL similar to previous works [16,[21][22][23]25] to perform two kinds of addition operations viz. dual-operand addition and multioperand addition.…”

Section: Heterogeneous/hybrid Csla Architecturesmentioning

confidence: 99%

“…Rather than realizing pure CSLAs, hybrid architectures incorporating carry select and carry lookahead structures have also been proposed [18][19][20][21] to improve the design efficiency of CSLAs. Moreover, some FPGA implementations of CSLAs have been attempted [21][22][23]. Overall, a survey of published literature reveals that CSLAs have been widely implemented using the following topologies and computational elements: In general, CSLAs are composed using a carry select architecture with/without BECs or may consist of a mix of carry select and carry lookahead configurations with/without BECs.…”

Section: Introductionmentioning

confidence: 99%

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FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Kokilavani

Preethi

Balasubramanian

2015

Advances in Electronics

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Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

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Section: Heterogeneous/hybrid Csla Architecturesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Kokilavani

Preethi

Balasubramanian

2015

Advances in Electronics

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“…Carry select adders are known for their speed. A low power consuming Carry select adder can be an asset for any SOI [3], [4], [6]. An efficient full adder design can been used to optimize the big designs.…”

Section: Previous Workmentioning

confidence: 99%

Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology

Murgai

Gupta

Muthukrishnan

2015

2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Arithmetic Logic Units are one of the vital unit in general purpose processors and major source of power dissipation. In this paper we have demonstrated an optimized Arithmetic and Logic Unit through the use of an optimized carry select adder. Carry select adders have been considered as the best in their category in terms of power and delay. In this context a full adder optimized in terms of power has been used in synthesizing a carry select adder. Combined with the new adder structure, there is a substantial improvement in terms of power and delay. The total device power and hierarchy power has been reduced to 12.5 % and 53.39 % respectively. 3 % reduction in total completion time has also been observed. The circuit has been synthesized on kintex FPGA through Xilinx 14.3 using 28 nm technology in Verilog HDL and results has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment.

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“…Owing to the rapid growth in system on chip industry, effective power utilization has become a major design constraint in large scale integration. To achieve this, a novel method has been proposed which makes use of universal NAND [9] gates in the conventional carry select adder by which the area, delay and hence the power delay product PDP has been reduced to a larger extent. The prime motive of this proposed work is to reduce the area and delay by proper manipulations in the carry select block.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction

Rachel¹,

Rajakumar.²

2019

IJEAT

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This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result helps to verify the effectiveness of the approach. This provides understanding on how the reduction of area can bring vital improvements in Very Large Scale Integration.

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Synthesis of carry select adder in 65 nm FPGA

Cited by 9 publications

References 10 publications

FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology

Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction

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