Synopsys' Educational Generic Memory Compiler

Goldman, Richard; Bartleson, Karen; Wood, Troy; Melikyan, Vazgen; Babayan, E.

doi:10.1109/ewme.2014.6877402

Cited by 9 publications

(4 citation statements)

References 5 publications

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Section: Background and Related Workmentioning

confidence: 99%

“…There are other memory compilation solutions [17] comparable to other companies' products [16]. Ass Generic Memory Compiler (GMC) [17] which is a tool designed to automatically generate multiple types of SRAM with different characteristics. offering a variety of capabilities and a simple user interface, very similar to those offered by other companies [16] for a wide number of configurations and architectures.…”

Section: Background and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Macro Memory Cell Generator for SKY130 PDK

Baungarten-Leon,

Ortega-Cisneros,

Pinedo-Diaz

et al. 2024

IEEE Access

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The SKY130 Process Design Kit (PDK) offers limited options for Static Random-Access Memory (SRAM) configurations, providing only three predefined memory sizes: 8×1024, 32×256, and 32×512, this poses a challenge for designers who require memories with different characteristics, as they must either design an entire memory architecture from scratch or resort to interleaving techniques with the available memory configurations. To address this issue, we present a novel framework that automates the generation of multiple memory arrays with custom floorplans, leveraging the concept of interleaving memory. Our framework enables designers to create various sizes and configurations memories by combining and interleaving the existing SKY130 PDK memories, additionally, the framework allows designers to easily specify their desired memory size, word length, floorplan, and other essential parameters. The framework then automatically generates multiple memory arrays that meet the specified requirements. Furthermore, it provides the files required by OpenLane, facilitating the seamless integration of these memories into the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow. The key advantage of our framework lies in its ability to streamline the creation of custom memories by automating the interleaving process and offering flexibility in floorplan design. This significantly reduces design time and effort, empowering designers to efficiently create memories with specific characteristics while adhering to the limitations of the SKY130 PDK. The framework thus serves as a valuable tool for memory design in the context of the SKY130 PDK, opening doors for more efficient and optimized chip designs.

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Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Macro Memory Cell Generator for SKY130 PDK

Baungarten-Leon,

Ortega-Cisneros,

Pinedo-Diaz

et al. 2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…In order to follow the contemporary rapid IC core design, which is supported via advanced EDA tools, memory compiler utilities [1][2][3] that accelerate and automate the production of SRAMS have been developed. With these utilities, the extraction of the memory's netlist along with power and timing reports is possible and, moreover, the extraction of the memory's layout view is an easy task.…”

Section: Introductionmentioning

confidence: 99%

Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model

Simopoulos

Alexiou

Haniotakis

2019

J CIRCUIT SYST COMP

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In this work, we extend the implementation guidelines of the WDSRAM — Write Driver SRAM — through the definition of a hierarchical implementation model which is applied on the material layout memory design level. This model can be used in order to create WDSRAMs of any size, maintaining the memory’s write function speed-up against the typical SRAM implementation model. The post-layout simulation results are presented in comparison with the corresponding results of the typical SRAM and confirm that the WDSRAM write function speed-up is maintained against the typical SRAM when the memory size increases. A brief background knowledge on the WDSRAM function is also provided.

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“…Another recent, promising solution for academia is the Synopsys Generic Memory Compiler (GMC) [7]. The software is provided with sample generic libraries such as Synopsys' 32/28nm and 90nm abstract technologies and can generate the entire SRAM for these technologies.…”

Section: Introductionmentioning

confidence: 99%

OpenRAM: an open-source memory compiler

Guthaus

Stine

Ataei

et al. 2016

Proceedings of the 35th International Conference on Computer-Aided Design

119

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Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial solutions only provide memory models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming and tedious and the designs are usually inflexible. This paper introduces OpenRAM, an open-source memory compiler, that provides a platform for the generation, characterization, and verification of fabricable memory designs across various technologies, sizes, and configurations. It enables research in computer architecture, system-on-chip design, memory circuit and device research, and computer-aided design.

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Synopsys' Educational Generic Memory Compiler

Cited by 9 publications

References 5 publications

Macro Memory Cell Generator for SKY130 PDK

Macro Memory Cell Generator for SKY130 PDK

Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model

OpenRAM: an open-source memory compiler

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