OpenRAM: an open-source memory compiler

Guthaus, Matthew R.; Stine, James E.; Ataei, Samira; Chen, Brian; Wu, Bin; Sarwar, Mehedi

doi:10.1145/2966986.2980098

Cited by 119 publications

(43 citation statements)

References 15 publications

(16 reference statements)

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“…Interestingly, most memories do not fit the exact required memory size, so they have empty space that may affect the area and delay estimates. Because of this, the results might be significantly better if the memory compiler could produce sizes that fit the required interpolator size more accurately, such as with some open-source memory compilers [45]. Designs were synthesized using Synopsys R Design Compiler TM and the layout was produced using Synopsys R IC Compiler (ICC) TM .…”

Section: Implementation Resultsmentioning

confidence: 99%

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers and cubers. Initial coefficient values are obtained using a Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized coefficient values to meet a user-specified error constraint. The algorithm minimizes coefficient lengths to reduce lookup table requirements, maximizes the number of truncated columns to reduce the area, delay and power of the arithmetic units, and minimizes the maximum absolute error of the interpolator output. The method can be used to design interpolators to approximate any function to a user-specified accuracy, up to and beyond 53-bits of precision (e.g., IEEE double precision significand). Linear, quadratic and cubic interpolator designs that approximate reciprocal, square root, reciprocal square root and sine are presented and analyzed. Area, delay and power estimates are given for 16, 24 and 32-bit interpolators that compute the reciprocal function, targeting a 65 nm CMOS technology from IBM. Results indicate the proposed method uses smaller arithmetic units and has reduced lookup table sizes compared to previously proposed methods. The method can be used to optimize coefficients in other systems while accounting for coefficient quantization as well as truncation and rounding effects of multiple arithmetic units.

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Section: Implementation Resultsmentioning

confidence: 99%

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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“…To address the slow single buffer delay, this paper proposed using both a fast uniform DWL topology and a fast, area-efficient non-uniform DWL topology. The non-uniform DWL topology uses an accurate analytical word line model that considers both gate and interconnect delays and can be used in a non-linear programming approach to enhance the performance of SRAMs word lines in memory compilers [1].…”

Section: Discussionmentioning

confidence: 99%

“…This paper focuses on detailed optimization of word line driver sizes and topologies in order to investigate the optimal word line driver configuration for a given memory size and technology. Such techniques can be included in memory compilers for high-performance memory variants [1]. A conventional word line driver using a single buffer topology is shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Fast and Area-Efficient SRAM Word-Line Optimization

Stine

Guthaus

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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A word line driver controls the access of cells in a row in Static Random Access Memories (SRAMs) and has a significant impact on SRAM speed and power consumption. When gate delay is the dominant factor, simple models are a good guideline for fast word lines. However, routing wire delay is significant when the row size is large, which causes these designs to be suboptimal. This paper presents an analytical optimization technique using a delay model that includes gate delay, wire resistance, and wire capacitance to optimize high-performance word line driver topologies for SRAMs. The proposed methodology has a maximum 45% delay improvement and 42% buffer cost reduction.

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“…The purpose of this work is to augment the OpenRAM [3] memory compiler with multi-port extensions. The contributions presented in this paper are:…”

Section: Introductionmentioning

confidence: 99%

Automated Synthesis of Multi-Port Memories and Control

Nichols

Grimes

Sowash

et al. 2019

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)

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High performance systems often employ multiported memories to enhance the throughput and flexibility of the memory. Existing SRAM compilers offer limited control over the SRAM design and port configurations while SRAMs are commonly dual-ported. Experimental designs could benefit from design exploration of multi-port configurations. We propose an open-source, multi-port solution that extends the OpenRAM memory compiler. A parameterized bitcell is presented which can support any combination of read, write, and read-write ports. The bitcell layout is generated for these port combinations, and the SRAM layout can support any combination of two ports. In addition, support for multi-port characterization and functional testing ensures correctness and incorporation into design methodologies.

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OpenRAM: an open-source memory compiler

Cited by 119 publications

References 15 publications

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

Fast and Area-Efficient SRAM Word-Line Optimization

Automated Synthesis of Multi-Port Memories and Control

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