SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures

Giannoula, Christina; Vijaykumar, Nandita; Παπαδοπούλου, Νικέλα; Karakostas, Vasileios; Fernández, Iván; Gómez-Luna, Juan; Orosa, Lois; Koziris, Nectarios; Goumas, Georgios; Mutlu, Onur

doi:10.1109/hpca51647.2021.00031

Cited by 40 publications

(17 citation statements)

References 114 publications

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“…Overestimating NDP Potential. Offloading kernels to NDP cores incurs overheads that our analysis does not account for (e.g., maintaining coherence between the host CPU and the NDP cores [50,52], efficiently synchronizing computation across NDP cores [136,143], providing virtual memory support for the NDP system [5,171,332], and dynamic offloading support for NDP-friendly functions [170]). Such overheads can impact the performance benefits NDP can provide when considering the end-to-end application.…”

Section: Limitations Of Our Methodologymentioning

confidence: 99%

“…We call this configuration Host CPU with prefetcher. • An NDP CPU with a single level of cache (only a private read-only 7 L1 cache (32 kB), as assumed in many prior NDP works [4,31,49,50,52,97,115,136,371,396]) and no hardware prefetcher. We call this configuration NDP.…”

Section: Scalability Analysis and Systemmentioning

confidence: 99%

“…In this work, we focus on generalpurpose NDP cores for two major reasons. First, many prior works (e.g., [4,31,49,50,90,97,115,125,136,251,260,301,334,371,396]) suggest that general-purpose cores (especially simple in-order cores) can successfully accelerate memory-bound applications in NDP architectures. In fact, UPMEM [94], a start-up building some of the first commercial in-DRAM NDP systems, utilizes simple in-order cores in their NDP units inside DRAM chips [94,143].…”

Section: Scalability Analysis and Systemmentioning

confidence: 99%

See 2 more Smart Citations

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

F.¹,

Gómez-Luna²,

Orosa³

et al. 2021

Preprint

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Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ a range of techniques to reduce overheads tied to data movement, spanning from traditional mechanisms (e.g., deep multi-level cache hierarchies, aggressive hardware prefetchers) to emerging techniques such as Near-Data Processing (NDP), where some computation is moved close to memory. Prior NDP works investigate the root causes of data movement bottlenecks using different profiling methodologies and tools. However, there is still a lack of understanding about the key metrics that can identify different data movement bottlenecks and their relation to traditional and emerging data movement mitigation mechanisms. Our goal is to methodically identify potential sources of data movement over a broad set of applications and to comprehensively compare traditional compute-centric data movement mitigation techniques (e.g., caching and prefetching) to more memory-centric techniques (e.g., NDP), thereby developing a rigorous understanding of the best techniques to mitigate each source of data movement.With this goal in mind, we perform the first large-scale characterization of a wide variety of applications, across a wide range of application domains, to identify fundamental program properties that lead to data movement to/from main memory. We develop the first systematic methodology to classify applications based on the sources contributing to data movement bottlenecks. From our large-scale characterization of 77K functions across 345 applications, we select 144 functions to form the first open-source benchmark suite (DAMOV) for main memory data movement studies. We select a diverse range of functions that (1) represent different types of data movement bottlenecks, and (2) come from a wide range of application domains. Using NDP as a case study, we identify new insights about the different data movement bottlenecks and use these insights to determine the most suitable data movement mitigation mechanism for a particular application. We open-source DAMOV and the complete source code for our new characterization methodology at https://github.com/CMU-SAFARI/DAMOV. CCS Concepts: • Hardware → Dynamic memory; • Computing methodologies → Model development and analysis; • Computer systems organization → Architectures.

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Section: Limitations Of Our Methodologymentioning

confidence: 99%

Section: Scalability Analysis and Systemmentioning

confidence: 99%

Section: Scalability Analysis and Systemmentioning

confidence: 99%

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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

F.¹,

Gómez-Luna²,

Orosa³

et al. 2021

Preprint

Self Cite

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“…Another body of recent works study and propose solutions to system integration challenges in PIM-enabled systems, such as memory coherence [27][28][29], virtual memory [86,96], synchronization [73], or PIM suitability of workloads [195].…”

Section: Related Workmentioning

confidence: 99%

Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture

Gómez-Luna¹,

Hajj²,

Fernández³

et al. 2021

Preprint

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Many modern workloads, such as neural networks, databases, and graph processing, are fundamentally memory-bound. For such workloads, the data movement between main memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bound workloads is insufficient to amortize the cost of main memory access. Fundamentally addressing this data movement bottleneck requires a paradigm where the memory system assumes an active role in computing by integrating processing capabilities. This paradigm is known as processing-in-memory (PIM).Recent research explores different forms of PIM architectures, motivated by the emergence of new 3Dstacked memory technologies that integrate memory with a logic layer where processing elements can be easily placed. Past works evaluate these architectures in simulation or, at best, with simplified hardware prototypes. In contrast, the UPMEM company has designed and manufactured the first publicly-available real-world PIM architecture. The UPMEM PIM architecture combines traditional DRAM memory arrays with general-purpose in-order cores, called DRAM Processing Units (DPUs), integrated in the same chip.This paper provides the first comprehensive analysis of the first publicly-available real-world PIM architecture. We make two key contributions. First, we conduct an experimental characterization of the UPMEM-based PIM system using microbenchmarks to assess various architecture limits such as compute throughput and memory bandwidth, yielding new insights. Second, we present PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domains (e.g., dense/sparse linear algebra, databases, data analytics, graph processing, neural networks, bioinformatics, image processing), which we identify as memory-bound. We evaluate the performance and scaling characteristics of PrIM benchmarks on the UPMEM PIM architecture, and compare their performance and energy consumption to their stateof-the-art CPU and GPU counterparts. Our extensive evaluation conducted on two real UPMEM-based PIM systems with 640 and 2,556 DPUs provides new insights about suitability of different workloads to the PIM system, programming recommendations for software designers, and suggestions and hints for hardware and architecture designers of future PIM systems. CCS Concepts: • Hardware → Dynamic memory; • Computing methodologies → Model development and analysis; • Computer systems organization → Architectures.

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“…Recent works propose a variety of PiM techniques to alleviate the data movement problem. One group of techniques propose to place compute capabilities near memory arrays [8][9][10]17,[21][22][23][24]28,30,32,34,[39][40][41]44,45,49,50,56,57,63,64,68,83,86,88,91,93,106,112,116,[118][119][120]. These techniques are called processing-near-memory (PnM).…”

Section: Introductionmentioning

confidence: 99%

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

Olgun¹,

Gómez-Luna²,

Kanellopoulos³

et al. 2021

Preprint

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Processing-using-memory (PuM) techniques leverage the analog operation of memory cells to perform computation. Several recent works have demonstrated PuM techniques (e.g., copy and initialization operations, bitwise operations, random number generation) in off-the-shelf DRAM devices. Since DRAM is the dominant memory technology as main memory in current computing systems, these PuM techniques represent an opportunity for alleviating the data movement bottleneck at very low cost. However, system integration of PuM techniques imposes non-trivial challenges (e.g., related to data allocation and alignment, memory coherence management) that are yet to be solved. Design space exploration of potential solutions to the PuM integration challenges requires appropriate tools to develop necessary hardware and software components. Unfortunately, current proprietary computing systems, specialized DRAM-testing platforms, or system simulators do not provide the flexibility and/or the holistic system view that is necessary to deal with PuM integration challenges.We design and develop PiDRAM, the first flexible endto-end framework that enables system integration studies and evaluation of real PuM techniques. PiDRAM provides software and hardware components to rapidly integrate PuM techniques across the whole system software and hardware stack (e.g., necessary modifications in the operating system, memory controller). We implement PiDRAM on an FPGAbased platform along with an open-source RISC-V system. To demonstrate the flexibility and ease of use of PiDRAM, we implement and evaluate two state-of-the-art PuM techniques. First, we implement in-memory copy and initialization. We propose solutions to integration challenges (e.g., memory coherence) and conduct a detailed end-to-end implementation study. Second, we implement a true random number generator in DRAM. Our results show that the in-memory copy and initialization techniques can improve the performance of bulk copy operations by 12.6× and bulk initialization operations by 14.6× on a real system. Implementing the true random number generator requires only 190 lines of Verilog and 74 lines of C code using PiDRAM's software and hardware components. PiDRAM is available on Github. 1

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SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures

Cited by 40 publications

References 114 publications

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

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