DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Abstract

Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ a range of techniques to reduce overheads tied to data movement, spanning from traditional mechanisms (e.g., deep multi-level cache hierarchies, aggressive hardware prefetchers) to emerging techniques such as Near-Data Processing (NDP), where some computation is moved close to memory. Prior NDP works investigate the root causes of data movement bottlenecks using different profiling methodologies and tools. However, there is still a lack of understanding about the key metrics that can identify different data movement bottlenecks and their relation to traditional and emerging data movement mitigation mechanisms. Our goal is to methodically identify potential sources of data movement over a broad set of applications and to comprehensively compare traditional compute-centric data movement mitigation techniques (e.g., caching and prefetching) to more memory-centric techniques (e.g., NDP), thereby developing a rigorous understanding of the best techniques to mitigate each source of data movement.With this goal in mind, we perform the first large-scale characterization of a wide variety of applications, across a wide range of application domains, to identify fundamental program properties that lead to data movement to/from main memory. We develop the first systematic methodology to classify applications based on the sources contributing to data movement bottlenecks. From our large-scale characterization of 77K functions across 345 applications, we select 144 functions to form the first open-source benchmark suite (DAMOV) for main memory data movement studies. We select a diverse range of functions that (1) represent different types of data movement bottlenecks, and (2) come from a wide range of application domains. Using NDP as a case study, we identify new insights about the different data movement bottlenecks and use these insights to determine the most suitable data movement mitigation mechanism for a particular application. We open-source DAMOV and the complete source code for our new characterization methodology at https://github.com/CMU-SAFARI/DAMOV. CCS Concepts: • Hardware → Dynamic memory; • Computing methodologies → Model development and analysis; • Computer systems organization → Architectures.

Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture

“…Hence, these workloads are all limited by memory. We conclude that all 14 CPU versions of PrIM workloads are potentially suitable for PIM [195]. We briefly describe each PrIM benchmark and its PIM implementation next.…”

“…However, an operational intensity of 1 64 OP/B is extremely low, as it entails only one addition for every 64 B accessed (16 32-bit integers). We expect higher operational intensity (e.g., greater than 1 4 OP/B) in most real-world workloads [195,248] and, thus, arithmetic throughput to saturate with 11 tasklets in real-world workloads.…”

“…Another body of recent works study and propose solutions to system integration challenges in PIM-enabled systems, such as memory coherence [27][28][29], virtual memory [86,96], synchronization [73], or PIM suitability of workloads [195].…”

Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures

“…We publicly release our 144 representative data movement bottlenecked functions from 74 applications as the first opensource benchmark suite for data movement, called DAMOV benchmark suite, along with the complete source code for our new characterization methodology and simulator [116]. For more information on our extensive data movement bottleneck characterization and on our DAMOV benchmark suite, along with our detailed contributions (including four use cases of our benchmark suite), please refer to our full paper [5,117].…”

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

“…Synergy With PIM. Processing-in-memory (PIM) systems improve system performance and/or energy consumption by performing computations directly within a memory chip, thereby avoiding unnecessary data movement [25,26,57,58,60,116,118,137,139]. Prior works propose a broad range of PIM systems [5-8, 13, 22-24, 34, 38, 44, 48, 49, 54, 55, 58, 59, 65, 66, 71, 72, 89, 98, 100, 103, 107, 113, 115, 119, 120, 124, 133-135, 137-139, 142, 148, 164, 168] in the context of various workloads and memory devices.…”