Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects

Chang, Kok-Leong; Chang, Joseph S.; Gwee, Bah-Hwee; Chong, Kwen-Siong

doi:10.1109/jetcas.2013.2243031

Cited by 41 publications

(30 citation statements)

References 25 publications

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“…A multi-platform communication system has been installed in a high-speed train, circulating at velocities up to 300 km/h, whereas autonomous devices have been disseminated along the railway path to communicate with the onboard devices. The Microcontrollers play a vital role in embodying intelligence into battery-powered everyday objects to realize the cooperative environment [41,42]. The desirable attributes of such a microcontroller and the like include high energy and area efficiency, and robust error-free operation under dynamic voltage scaling (DVS), workload, process, voltage, and temperature (PVT) variation effects.…”

Section: Related Workmentioning

confidence: 99%

Cooperative Intelligence of Vehicles for Intelligent Transportation Systems (ITS)

Daniel

Paul

Ahmad

et al. 2015

Wireless Pers Commun

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The aim of Intelligent Transportation Systems (ITS) is to automate the interactions among vehicles and infrastructure to accomplish high levels of safety measures, comfort, and competence in vehicular communication. To utilize the future trends of increasing traffic safety and efficiency in ITS, integrating vehicles and infrastructures with the cooperative vehicular technique will be the feasible solution. In order to demonstrate the importance of cooperative communication in vehicular networks, a spectral efficient architecture has been proposed for cooperative centralized and distributed spectrum sensing in vehicular networks. We discuss the possibilities of Cognitive Radio in the cooperative vehicular environment. In order to exhibit cooperative vehicular networks, hardware modules are designed for a vehicle to vehicle, vehicle to infrastructure and infrastructure to infrastructure communications. Furthermore, quantitative analysis is made in order to calculate the energy optimization, connectivity failure probability and traffic management in cooperative vehicular networks. In addition, we test the results of the cooperative vehicular network by simulating it in NS2. In this respect, we have considered three different cases, Emergency vehicles, VIP vehicles, and normal vehicles. It is inferred from the results that end-to-end delay for emergency vehicles in the cooperative environment is considerably less as compared to VIP and normal vehicles.

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Section: Related Workmentioning

confidence: 99%

Cooperative Intelligence of Vehicles for Intelligent Transportation Systems (ITS)

Daniel

Paul

Ahmad

et al. 2015

Wireless Pers Commun

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“…[4]. In this backdrop, an asynchronous design method that is modular and which can innately cope with arbitrary variations in processes or parameters is preferable [5][6][7]. Such an asynchronous design method corresponds to the input-output timing model [8], which utilizes delay-insensitive codes for data encoding (i.e., representation) and processing and adheres to the 4-phase return-to-zero (RTZ) or return-to-one (RTO) handshake protocol for data communication.…”

Section: Introductionmentioning

confidence: 99%

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

2018

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

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“…This explains the continued popularity of the device. Applications of the 8051 microcontroller encompass a wide range of technical areas, including embedded systems, robotics, and telecommunications (Chang et al, 2013;Kanniga & Sundarajan, 2015;Jain et al, 2013;Pahuja & Kumar, 2014;Arsalan, 2013).…”

Section: Introductionmentioning

confidence: 99%

Vlsi Circuit Optimization for the 8051 Mcu

Yeap¹,

Thee²,

Lai³

et al. 2018

IJTech

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With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5-µm process technology. Hence, the device is slow and the chip size is large. To enhance the performance of the device and to minimize the die size, we used 90-nm technology in our design. We first performed optimization when mapping the RTL codes with the 90 nm standard cell libraries. Once the gate level netlist was generated, we developed the layout of the device by going through floor-planning, placement, and routing. We show that our new design is capable of operating at 150 MHz (i.e., 12.5 times faster than the original design), with a significant reduction in chip size (i.e., the total area is 77249.814850 µm 2 ). The power consumption of the chip is 593.9899 µW, which is at least 32% lower than that of other 8051 derivatives.

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Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects

Cited by 41 publications

References 25 publications

Cooperative Intelligence of Vehicles for Intelligent Transportation Systems (ITS)

Cooperative Intelligence of Vehicles for Intelligent Transportation Systems (ITS)

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Vlsi Circuit Optimization for the 8051 Mcu

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