Synchronous chip-to-chip communication with a multi-chip resonator clock distribution network ^*

Abstract

Superconducting digital circuits are a promising approach to build packaged-level integrated systems with high energy-efficiency and computational density. In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance. In this work we report a synchronous data link using Reciprocal Quantum Logic (RQL) enabled by resonant clock distribution on the chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300W/W cooling overhead. The driver produces a signal with 35 GHz analog bandwidth and connects to a single-ended receiver via 20 Ω Nb Passive Transmission Line (PTL). To validate this link, we have designed, fabricated and tested two 32 x 32mm2 MCMs with eight 5 x 5mm2 chips connected serially and powered with a meander clock, and with four 10 x 10mm2 chips powered with a 2 GHz resonant clock. The meander clock MCM validates performance of the data link components, and achieved 5.4 dB AC bias margin with no degradation relative to individual chip test. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate.

Properties of Nb x Ti(1−x)N thin films deposited on 300 mm silicon wafers for upscaling superconducting digital circuits

“…Relative to Nb, Nb x Ti (1−x) N can achieve a 1.8× higher critical temperature up to 17.3 K, and a 1.8× higher gap voltage [23]. This improves the analog bandwidth and reach of passive transmission line (PTL) interconnects in digital logic [24,25] and raises the I c R n product of the Josephson junctions. The high kinetic inductance of Nb x Ti (1−x) N enables physically small, fixed-inductance interconnects without meanders while minimizing parasitic mutual inductance arising from larger geometries.…”

Design and Simulation of Phase Synchronizer for Adiabatic Quantum Flux Parametron Circuits

“…This inherent synchrony presents a practical barrier to scaling to large systems due to the accumulation of phaseskew across designs of moderate size and complexity as the wavelength of the clock becomes comparable to the length of some interconnect paths. This problem is well known in the CMOS and superconductor electronics (SCE) communities, and has been a subject of active research since the advent of clocked systems [7]- [11]. On the scale of single-chip designs, a phase synchronizer is highly desirable to allow resilience against the significant timing uncertainty in crosschip connections [5].…”