We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux-Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.

No abstract

We experimentally demonstrate the operation of a Josephson magnetic random access memory unit cell, built with a Ni80Fe20/Cu/Ni pseudo spin-valve Josephson junction with Nb electrodes and an integrated readout SQUID in a fully planarized Nb fabrication process. We show that the parallel and anti-parallel memory states of the spin-valve can be mapped onto a junction equilibrium phase of either zero or π by appropriate choice of the ferromagnet thicknesses, and that the magnetic Josephson junction can be written to either a zero-junction or π-junction state by application of write fields of approximately 5 mT. This work represents a first step towards a scalable, dense, and power-efficient cryogenic memory for superconducting high-performance digital computing.

Articles you may be interested inA pulsed-power generator merging inductive voltage and current adders and its switch trigger application example Rev. Sci. Instrum. 84, 075108 (2013); 10.1063/1.4812694Towards constructing multi-bit binary adder based on Belousov-Zhabotinsky reaction A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy Appl. Phys. Lett.Reciprocal quantum logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2 GHz. Latency is only 150 ps at a clock rate of 10 GHz. V C 2013 American Institute of Physics.

We report the design and test of reciprocal quantum logic shift-register yield vehicles consisting of up to 72 800 Josephson junction devices per die, the largest digital superconducting circuits ever reported. Multiple physical layout styles were matched to the MIT Lincoln Laboratory foundry, which supports processes with both four and eight metal layers and minimum feature size of 0.5 μm. The largest individual circuits with 40 400 junctions indicate large operating margins of ±20% on ac clock amplitude. In one case the data were reproducible to the accuracy of the measurement, ±1% across five thermal cycles using only the rudimentary precautions of passive mu-metal magnetic shielding and a controlled cool-down rate of 3 mK s−1 in the test fixture. We conclude that with proper mitigation techniques, flux-trapping is no longer a limiting consideration for very-large-scale-integration of superconductor digital logic.