Symmetric and Excellent Scaling Behavior in Ultrathin n‐ and p‐Type Gate‐All‐Around InAs Nanowire Transistors

Abstract

Complementary metal‐oxide‐semiconductor (CMOS) field‐effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µe than silicon but suffers from a much lower hole mobility µh (µe/µh = 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum‐transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub‐2‐nm‐diameter gate‐all‐around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short‐channel effects are effectively depressed in the symmetric n‐ and p‐type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits.

Sub-5 nm Gate-All-Around InP Nanowire Transistors toward High-Performance Devices

“…The superior scaling behavior of the Si NW, CNT, and ML InP compared to that of the InP NW is mainly attributed to the smaller electron m *. As revealed by previous studies, ,,− the relationship between I on and m * can be explained from two aspects. On the one hand, a large m * results in a small electron velocity ( v ) and thus a small I on ( I on ∝ v ∝ 1 m * ).…”

“…First, to our best knowledge, the investigation of III−V material NW FETs with ultrashort L g (<10 nm) and ultranarrow D NW (<10 nm) remains rarely reported so far except for the InAs NW FETs. 51 This work thus provides potentially useful insights into the computational design and performance of ultrasmall III−V material NW FETs. Second, the search for channel candidates that are suitable for the sub-10 nm devices in terms of ITRS standards is a key challenge that needs to be addressed urgently.…”

“…However, the investigation of ultrasmall-scale InP NW devices remains important due to the following two aspects. First, to our best knowledge, the investigation of III–V material NW FETs with ultrashort L g (<10 nm) and ultranarrow D NW (<10 nm) remains rarely reported so far except for the InAs NW FETs . This work thus provides potentially useful insights into the computational design and performance of ultrasmall III–V material NW FETs.…”

“…51 On the other hand, for the ultrasmall nanowire system, the presence of QCE enhances the intersubband separation and thus reduces the intersubband scattering, increasing the corresponding mobility. 51,63 Indeed, the fieldeffect mobility of the nanowire FETs is proven to be reversely proportional to the D NW . Overall, when reducing D NW , the device performance of the nanowire FETs is determined by the interplay between m* and mobility modulations induced by QCE.…”

“…For example, it is demonstrated that the electron m * of wurtzite-phase InAs nanowire is increased when reducing D NW ( m * increases from 0.07 to 0.97 m 0 with D NW reducing from 3.1 to 0.8 nm) . On the other hand, for the ultrasmall nanowire system, the presence of QCE enhances the intersubband separation and thus reduces the intersubband scattering, increasing the corresponding mobility. , Indeed, the field-effect mobility of the nanowire FETs is proven to be reversely proportional to the D NW . Overall, when reducing D NW , the device performance of the nanowire FETs is determined by the interplay between m * and mobility modulations induced by QCE.…”