Sub-5 nm Gate-All-Around InP Nanowire Transistors toward High-Performance Devices

Abstract

The gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability compared to that of the conventional FinFET architecture. The significantly higher electron mobility of indium phosphide (InP) NW than that of silicon NW makes it particularly well-suited for high-performance (HP) electronic applications. In this work, we perform an ab initio quantum transport simulation to investigate the performance limit of sub-5 nm gate length (L g ) GAA InP NW FETs. The GAA InP NW FETs with L g = 4 nm can meet the International Technology Roadmap for Semiconductors (ITRS) requirements for HP devices from the perspective of onstate current, delay time, and power dissipation. We also investigate the impact of strain on 3 nm-L g GAA InP NW FETs. The application of tensile strain results in a remarkable improvement in the corresponding device's performance. These results highlight the potential of GAA InP NW FETs for HP applications in the sub-5 nm L g region.