Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges

Linearity and Analog Performance Realization of Energy-Efficient TFET-Based Architectures: An Optimization for RFIC Design

“…Keeping this in view, investigation of edge TFETs for further in wireless domain has continued and therefore, an attempt has been made with our previously proposed architecture, i.e., DMG (dual material gate) H-D (hetero-dielectric) TFET [6,14] having better analog performance than H-D TFET and better digital performance than both DMG TFET and H-D TFET. The present work focuses on the analog and linearity performance assessment of the above-mentioned three device architectures (shown in Figure 1) for RF/analog applications.…”

“…In this regime, researchers have explored many improved TFET architectures [5À14] (both edge-as well as area-scaled TFETs), which have shown significant improvement in terms of I on /I off ratio, suppressed SS, lower threshold voltage (V th ), suppressed ambipolar behaviour, and parasitic capacitance values. However, in past years there have been material engineered as well as gate work function engineered architectures reported [4À6, 11,12,14] which are edge TFETs only, and help in achieving the essential requirements for low-power applications. These reported edge TFETs [3,5] have silicon as channel material, coupled with asymmetric dielectric material combination (high-k near source side and low-k near drain side) between gate and the channel.…”

Analytical modelling of dielectric engineered strained dual‐material double‐gate‐tunnelling field effect transistor

“…Power dissipation is a major concern for traditional MOSFETs to be realised in nanoscale domain. Excersing the option of lowering supply voltage may lead to exponential increase in leakage current owing to the fact that transport mechanism is devised by carrier diffusion over a thermal barrier which is limited to 60 mV/decade [1]. Available research literatures testify the fact that tunneling field effect transistors (TFETs) by virtue of their reliability, low OFF‐state leakage current, ability to achieve sub‐threshold swing (SS) below the limiting value of 60 mV/dec and reduced short channel effect (SCE)s (due to built‐in tunnelling of electrons) can be regarded as a suitable alternative device to MOSFETs for low power and ultra‐low voltage applications [2, 3].…”