Switching activity estimation for shift-and-add based constant multipliers

Abstract

In this work we propose a switching activity model for single adder multipliers. This correspond to the case where a signal is added to a shifted version of itself, which is a common part in multiple constant multiplication (MCM). Hence, the proposed model is suitable to be used in power consumption aware MCM algorithms. The model is shown to agree well with simulations, and for the studied test cases a maximum error of 0.26% is obtained.

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

“…The constant multiplications referred here are expressed in fixed-point arithmetic because implementations in this number representation have higher speed and lower cost, thus being usually employed in DSP algorithms [30][31][32][33][34][35][36][37][38][39][40]. Only integer, positive, odd constants are considered since this is a useful simplification that does not affect the formulation of constant multiplication problems.…”

“…The MCM is built upon SCM because the latter is the simplest case. The SCM array is represented using directed acyclic graphs (DAGs) with the following characteristics [33][34][35][36]:…”

Estimation of the switching activity in shift-and-add based computations

“…As concluded in [11], timing must be taken into account when modeling the switching activity for constant multiplication. The idea here is to handle each event, i.e., each possible change of any FA input, separately.…”

4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

“…For the twiddle factor multipliers with small ranges special methods have been proposed. Especially, one can note that for a W 4 multiplier the possible coefficients are {±1, ±j} and, In digital CMOS circuits, dynamic power is the dominating part of the total power consumption which can be approximated by [9] P…”