4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

Abstract

Abstract-In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on FieldProgrammable Gate Arrays(FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

Area-Efficient Scheduling Scheme Based FFT Processor for Various OFDM Systems

“…The twiddle factor is is not required. The twiddle factor multiplication is one of the major contributors to the area of the FFT processor, which requires both memories and complex multipliers [15]. The existing processor [10] requires ROMs with 1024 stored words.…”

Improvement on Fpga Implementation of a Pipeline Large-FFT Processor

“…Its architecture includes the Radix22 single-path delay feedback (SDF) decimation in frequency (DIF) 4096-point FFT with a maximum operating frequency of 121.2 MHz. There are other studies to reduce the circuit complexity with algorithms to minimize the size and power of the FFT processor using coefficient memory reduction [8] [9] and switching activity analysis schemes [10] [11]. The architecture of Radix-22 SDF DIF N-point FFT [12] is considered as one with the least hardware resource requirement [13] in ultra-wideband scanning.…”