Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Horiguchi,; Sakata,; Itoh,

doi:10.1109/vlsic.1993.920533

Cited by 40 publications

(14 citation statements)

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“…In the present design, the steady state current was significantly lower than the threshold voltage current of the MOSFET. However, in high-density chips, the current could be suppressed to a significant level by the use of the switched source impedance method [14].…”

Section: Resultsmentioning

confidence: 99%

A Fast ALU Design in CMOS for Low Voltage Operation

Srivastava

Govindarajan

2001

VLSI Design

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A high-speed 4-bit ALU has been designed for 1 V operation to demonstrate the usefulness of the backgate forward substrate bias (BGFSB) method in 1.2 mm N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations -four arithmetic and four logical operations. The BGFSB voltage has been limited to j0.4j V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2 -2.5 is obtained with BGFSB over the conventional design.

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Section: Resultsmentioning

confidence: 99%

A Fast ALU Design in CMOS for Low Voltage Operation

Srivastava

Govindarajan

2001

VLSI Design

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“…To the best of our knowledge, the importance of reducing subthreshold currents in low-voltage high-speed room-temperature operation LSIs only became apparent in 1991 [9] as a result of innovative developments with 1.5-V high-speed DRAMs [10,11]. In addition to the preceding reduction schemes through dynamic substrate control and power switches [12], other key solutions to reduce subthreshold current were proposed in the early 1990s [13][14][15][16][17], although these were all in the standby mode. A solution to reduce subthreshold current in the active mode was presented as early as 1993 using a hypothetical 16-Gb DRAM [18].…”

Section: ]mentioning

confidence: 99%

“…Here, the V GS reverse biasing scheme can be further categorized as V S -control with a fixed V G (A1) [14,15] and V G -control with a fixed V S (A2) [13]. The V BS reverse biasing schemes can be categorized as V B -control with a fixed V S (B1) [12,50] and V S -control with a fixed V B (B2) [51,52].…”

Section: Reduction Of Subthreshold Current In Peripheral Circuitsmentioning

confidence: 99%

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Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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“…487494 added to increase the drive current beforehand in the time span while the circuit is operating. Methods that supply power only in the time span while the circuit is operating include circuits [4] that use the switch circuits to raise the source voltage during standby and decrease the off current, and circuits [5] that adjust the substrate potential of the MOSFET to reduce the off current.…”

Section: Introductionmentioning

confidence: 99%

A high‐speed, low‐power SOI CMOS circuit with variable threshold voltages

Higuchi¹,

Ikeda²

2001

Electron. Comm. Jpn. Pt. II

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SUMMARYWe have proposed a high-speed, low-power CMOS circuit that controls the substrate voltage of the SOI MOS-FET by the output voltage of a CMOS inverter circuit. This circuit operates at a power supply voltage of 1 V or lower with a nearly constant delay for rise times and fall times of the input signal from 10 ps to 500 ps and has a maximum reduction of 60% in the delay time compared to a conventional circuit. We defined the structure to speed up this circuit and illustrated the relationship between the MOS-FET device parameters and the circuit characteristics. The power consumption during standby in this circuit can be reduced to 1 nW by adjusting the supply voltage to the MOSFET substrate. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(5) : 2028, 2001

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Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Cited by 40 publications

References 0 publications

A Fast ALU Design in CMOS for Low Voltage Operation

A Fast ALU Design in CMOS for Low Voltage Operation

Review and future prospects of low-voltage RAM circuits

A high‐speed, low‐power SOI CMOS circuit with variable threshold voltages

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