Review and future prospects of low-voltage RAM circuits

Abstract

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed

“…Leakage power consumption is well known to be a major issue in the design of nanometer VLSI circuits [1], [2]. Cache memories are particularly sensitive to leakage for various reasons.…”

“…Secondly, the cache power consumption often represents a considerable portion of the overall chip power and area, especially in high-performance embedded processors [3], [4], [5]. Thirdly, at each new technology node, the leakage power is increasing faster than the dynamic power [1], [2]. For these reasons, new techniques to reduce leakage of caches are continuously required.…”

“…In the last decade, various techniques to reduce leakage in caches were devised at the boundary of circuit and architectural level [2]- [4]. Among these approaches, various techniques were proposed that dynamically vary the supply voltage of each cache line depending on whether it operates in active mode (normal operation, high leakage) or standby mode (not immediately accessible, low leakage).…”

Nanoscale CMOS circuit leakage power reduction by double-gate device

“…With a thinner gate oxide, more gate tunneling current occurs. For gate-oxide thickness below 1 nm, high-K dielectric materials with thicker layer than SiO 2 must be used to reduce gate leakage [2,3,4]. However, it significantly reduces carrier mobility, thereby degrading CMOS performance [5].…”

“…However, it significantly reduces carrier mobility, thereby degrading CMOS performance [5]. Circuit design techniques to mitigate the impact of gate leakage would be much less efficient than the use of high-K material since gate leakage is a stronger function of process-induced oxide thickness fluctuation as compared to change in V DD and threshold voltage [4]. In addition to the gate-oxide scaling issue, higher doping concentrations would degrade subthreshold swing (S).…”