Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed

Abstract

In this paper, a technique to reduce the leakage power consumption in embedded drowsy instruction caches (I caches) is proposed. The technique is called "Improved Drowsy" (ID), and adopts a more efficient strategy than standard Drowsy Caches (DCs) to turn off unused cache lines, based on locality. The implementation of ID caches requires minor changes, and the area/speed overhead associated with the additional circuitry is insignificant. The proposed technique is assessed through circuit and cycle accurate simulations on an L1 instruction cache embedded in an ARM XScale processor based system in a 65 nm CMOS technology. Results show that this technique is able to reduce the leakage power by 69% on average. Leakage of DC is shown to be significantly lowered with the proposed ID approach, being DC leakage greater than that of ID by up to 53%, and 10 15% typically.

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management

“…Alioto et al [31] have proposed a scheme to exploit locality wherein they put active lines to drowsy mode immediately after the access moves on to another line. They have devised localized control, based on the observation that the newly accessed cache lines are nearby to the previously accessed line (spatial locality).…”

“…As mentioned in Section 2, Alioto et al [31] have proposed a scheme where they put active lines to drowsy mode immediately after the access moves on to another line. The authors have named it the Improved Drowsy scheme, which is an improvement over the scheme proposed by Flautner et al [3].…”

“…In the proposed Improved Drowsy scheme [31], along with this global update signal, every cache line has four other drowsy signals. The cache line gets drowsy signals from two lines above and below it.…”

Early wakeup: improving the drowsy cache performance

“…Several research groups have focused on the drowsy cache [4][5][6][7]. Research dealing with the drowsy cache has mainly focused on the energy reduction, while this work focuses on the performance improvement of the drowsy cache by reducing the extra cycles to wake up the drowsy cache lines.…”

“…For instruction caches, a wakeup prediction technique based on branch prediction was proposed [6], which is not applicable to data caches. The improved drowsy (ID) technique, which determines the states of cache lines based on the locality, was proposed to improve the efficiency of the drowsy instruction cache [7]. The ID technique also cannot be applied to the drowsy data cache because the locality of the data cache is worse than that of the instruction cache.…”