A high‐speed, low‐power SOI CMOS circuit with variable threshold voltages

Abstract

SUMMARYWe have proposed a high-speed, low-power CMOS circuit that controls the substrate voltage of the SOI MOS-FET by the output voltage of a CMOS inverter circuit. This circuit operates at a power supply voltage of 1 V or lower with a nearly constant delay for rise times and fall times of the input signal from 10 ps to 500 ps and has a maximum reduction of 60% in the delay time compared to a conventional circuit. We defined the structure to speed up this circuit and illustrated the relationship between the MOS-FET device parameters and the circuit characteristics. The power consumption during standby in this circuit can be reduced to 1 nW by adjusting the supply voltage to the MOSFET substrate. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(5) : 2028, 2001

A study of the occurrence mechanism for undershoot of logic signal

“…In particular, the hysteresis type [1], overshoot type [2], and undershoot type of transient waveform distortion of logic signals have been causing problems. Efforts to deal with these problems have included a high-speed, low-power CMOS circuit with variable threshold voltages [3], a method of alleviating transient signal distortion [4], and device immunity evaluation for undershoot [5]. Figure 1 shows an observed waveform with undershoot.…”