Switched capacitor, self referencing sensing scheme for high density magneto-resistive memories

Abstract

CHAPTER 1. INTRODUCTION 1 1.1 Review of Storage Technologies 1 1.2 Evaluation of Different Storage Technologies 8 CHAPTER 2. THE MAGNETO-RESISTIVE ELEMENT 12 2.1 Magneto-Resistance 12 2.2 Magneto-Resistive Material Used 12 2.3 Structure and Fabrication of the Magneto-Resistive Element 13 2.4 The Magnetic Field in the Element 15 2.5 Read and Write in the Magneto-Resistive Element 17 CHAPTER 3. THE MAGNETO-RESISTIVE MEMORY 22 3.1 The Block Diagram 22 3.2 The Magneto-Resistive Element Array 22 CHAPTER 4. PROBLEMS IN SENSING 28 4.1 Change in Element Resistance due to Heating 28 4.2 Mismatch Between the Sense Lines and the Dummy line due 28 to Process Variations 4.3 Noise 29 iii 4.4 Differences in Heating Time Constants of Elements 30 CHAPTER 5. OVERVIEW OF THE SENSING SCHEME 32 CHAPTER 6. BALANCED SENSING 35 6.1 Problems of the Old Scheme 35 6.2 New Scheme 37 CHAPTER 7. AUTO-ZERO 40 7.1 Principle of Operation 7.2 Signal to Noise Ratio Calculation for Auto-Zero 7.3 Single Stage Auto-Zlero Scheme 7.4 Two Stage Auto-Zero Scheme CHAPTER 8. DIFFERENTL\L TO SINGLE CONVERTER AND BANDWIDTH LIMITER 8.1 Differential to Single Converter 53 8.2 Bandwidth Limiter 53 CHAPTER 9. SAMPLE AND HOLD 57 9.1 Sample and Compare Method 57 9.2 Capacitor Construction 61 CHAPTER 10. SPECIFICATIONS OF THE IMBIT MAGNETO-63 RESISTIVE MEMORY AND THE SENSING SCHEME CHAPTER 11. CONCLUSION 72

A low-noise small signal sensing scheme in voltage mode for high density magnetoresistive memories

“…The other stages are described in reference [11]. A detailed explanation of the timing diagrams is given in reference [11].…”

“…This is done by going into a new "self referencing" scheme which reduces the cell array area by a factor of 2 by eliminating the ping pong matching array [11]. In effect, it compares a bit 'zero' signal with a bit 'one' signal obtained from the same memory cell.…”

“…Among the contributions are an improved logical organization of bit arrays with buried transistors, redundancy schemes [3], and a new sensing technique which uses voltage mode small signal sensing and self referencing [11] to improve the density and accommodate future low voltage operation.…”

“…Then the signal is fed to a sample and hold circuit which holds the first sample (obtained with positive sense current), and compares with the second sample (obtained with negative sense current), to produce a logic level output [11].…”

“…The bandwidth limiter circuit sets the system bandwidth to 5 MHz in order to limit thermal noise [11]. …”