Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets

Abbasitabar, Hamed; Zarandi, Hamid R.; Salamat, Ronak

doi:10.1109/iccse.2012.81

Cited by 13 publications

(7 citation statements)

References 10 publications

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“…The results reveal that using TMR in SRAM-based FPGA without scrubbing [5], the percentage of the sensitive bits is about 4.65% while in this paper using a TMR in IU, the sensitive bits represent 3.19% of the total bits.…”

Section: B Analysis Of Seu Mitigation On Leon3's Program Countermentioning

confidence: 81%

“…In [5], injection of SEU, SET and MBU faults have been done in many components of LEON3, showing that integer unit and multiplier unit are more susceptible against SEU and MBU fault injection.…”

Section: Introductionmentioning

confidence: 99%

“…In previous works, the PC of LEON3 was not evaluated in point of sensitivity because to its important function in system security, in addition, based on the work in [5] avowed that the integer unit is the most critical block of LEON3 to SEU and MBU fault injection. The principal goal in this paper is to give the benefits of SEU mitigation for the LEON3 processor on the PC by adding a repair technique of fault tolerant like a TMR in this work.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Kchaou¹,

Youssef²,

Tourki³

2017

ijacsa

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Section: B Analysis Of Seu Mitigation On Leon3's Program Countermentioning

confidence: 81%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Kchaou¹,

Youssef²,

Tourki³

2017

ijacsa

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“…This section depicts the developed fault injection module for RTL descriptions, similar to that presented in [11,28]. The main distinction between FIMs is the moment in which the fault is injected.…”

Section: Fault Injection Methodologymentioning

confidence: 99%

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Abich

Garibotti

Bandeira

et al. 2021

IET Computers & Digital Tech

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Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high‐charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just‐in‐time fault injection simulator (OVPsim‐FIM) against fault injection campaigns conducted with event‐driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single‐core fault injection campaigns are performed on RTL descriptions of Arm Cortex‐M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex‐A9 scenarios. Campaigns consider different open‐source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim‐FIM is more than 1000× faster than cycle‐accurate simulators and up to 312× faster than event‐driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.

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“…Vice versa, the MEU-mp is induced by several particle hits that are typically obtained after long time radiation exposure. This accumulation scenario is characterized by multiple memory cells modification in various locations [11]. The main contribution of this work consists on the fault tolerance analysis of different TMR benchmarks implemented on the new generation of SRAM-based FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

Sterpone

Boragno

2017

2017 IEEE 23rd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high performance and design flexibility. In particular, for aerospace and avionics application fields, SRAM-based FPGAs are increasingly adopted for their configurability features making them a viable solution for long-time applications. However, these fields are characterized by a radiation environment that makes the technology extremely sensitive to radiation-induced Single Event Upsets (SEUs) in the SRAM-based FPGA's configuration memory. Configuration scrubbing and Triple Modular Redundancy (TMR) have been widely adopted in order to cope with SEU effects. However, modern FPGA devices are characterized by a heterogeneous routing resource distribution and a complex configuration memory mapping causing an increasing sensitivity to Cross Domain Errors affecting the TMR structure. In this paper we developed a new methodology to calculate the reliability of TMR architecture considering the intrinsic characteristics of the new generation of SRAM-based FPGAs. The method includes the analysis of the configuration bit sharing phenomena and of the routing long lines. We experimentally evaluate the method of various benchmark circuits evaluating the Mean Upset To Failure (MUTF). Finally, we used the results of the developed method to implement an improved design achieving 29x improvement of the MUTF.

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Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets

Cited by 13 publications

References 10 publications

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

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