SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Kchaou, Afef; Youssef, Wajih El Hadj; Tourki, Rached

doi:10.14569/ijacsa.2017.080737

Cited by 1 publication

(1 citation statement)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are many traditional system-level SEU mitigation methods [12,13]; however, due to the large computational requirements and numerous parameters of CNNs, these system mitigation methods are not well suited for CNN hardening needs. On the one hand, the significant number of weight parameters in CNNs occupies a large portion of the storage resources in onboard hardware accelerators, causing the Full-TMR methods to exacerbate the already limited hardware resources.…”

Section: Introductionmentioning

confidence: 99%

Evaluation and Mitigation of Weight-Related Single Event Upsets in a Convolutional Neural Network

Cai,

et al. 2024

Electronics

View full text Add to dashboard Cite

Single Event Upsets (SEUs) are most likely to cause bit flips within the trained parameters of a convolutional neural network (CNN). Therefore, it is crucial to analyze and implement hardening techniques to enhance their reliability under radiation. In this paper, random fault injections into the weights of LeNet-5 were carried out in order to evaluate and propose strategies to improve the reliability of a CNN. According to the results of an SEU fault injection, the accuracy of the CNN can be classified into the following three categories: benign conditions, poor conditions, and critical conditions. Two efficient methods for mitigating weight-related SEUs are proposed, as follows: weight limiting and Triple Modular Redundancy (TMR) for the critical bit of the critical layer. The hardening results show that when the number of SEU faults is small, the weight limiting almost completely eliminates the critical and poor conditions of LeNet-5’s accuracy. Additionally, even when the number of SEU faults is large enough, combining the weight limiting and TMR methods for the critical bit of the critical layer can retain the occurrence rate of benign conditions at 98%, saving 99.3% of the hardware resources compared to the Full-TMR hardening method.

show abstract

Section: Introductionmentioning

confidence: 99%